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coreboot: introduce commonlib 

Instead of reaching into src/include and re-writing code
allow for cleaner code sharing within coreboot and its
utilities. The additional thing needed at this point is
for the utilities to provide a printk() declaration within
a <console/console.h> file. That way code which uses printk()
can than be mapped properly to verbosity of utility parameters.

Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11592
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Aaron Durbin 2015-09-08 13:34:43 -05:00
parent 4b93a4f47a
commit dc9f5cd546
85 changed files with 619 additions and 582 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Makefile.inc
View File

@ -54,7 +54,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs
#######################################################################
# root source directories of coreboot
subdirs-y := src/lib src/console src/device src/acpi
subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi
subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode
@ -267,7 +267,7 @@ ifneq ($(CONFIG_LOCALVERSION),"")
export COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))
endif
CPPFLAGS_common := -Isrc -Isrc/include -I$(obj)
CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj)
CPPFLAGS_common += -Isrc/device/oprom/include
CPPFLAGS_common += -include $(src)/include/kconfig.h

2
src/arch/x86/include/arch/cbfs.h
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@ -20,7 +20,7 @@
#ifndef __INCLUDE_ARCH_CBFS__
#define __INCLUDE_ARCH_CBFS__
#include <cbfs_serialized.h>
#include <commonlib/cbfs_serialized.h>
#include <endian.h>
#define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) )

2
src/arch/x86/romcc_console.c
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@ -20,7 +20,7 @@
#include <build.h>
#include <console/streams.h>
#include <console/early_print.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
/* Include the sources. */
#if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO

10
src/commonlib/Makefile.inc Normal file
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@ -0,0 +1,10 @@
bootblock-y += mem_pool.c
verstage-y += mem_pool.c
romstage-y += mem_pool.c
ramstage-y += mem_pool.c
bootblock-y += region.c
verstage-y += region.c
romstage-y += region.c
ramstage-y += region.c
smm-y += region.c

0
src/include/cbfs_serialized.h → src/commonlib/include/commonlib/cbfs_serialized.h
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0
src/include/cbmem_id.h → src/commonlib/include/commonlib/cbmem_id.h
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387
src/commonlib/include/commonlib/coreboot_tables.h Normal file
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@ -0,0 +1,387 @@
#ifndef COMMONLIB_COREBOOT_TABLES_H
#define COMMONLIB_COREBOOT_TABLES_H
#include <stdint.h>
/* The coreboot table information is for conveying information
* from the firmware to the loaded OS image. Primarily this
* is expected to be information that cannot be discovered by
* other means, such as querying the hardware directly.
*
* All of the information should be Position Independent Data.
* That is it should be safe to relocated any of the information
* without it's meaning/correctness changing. For table that
* can reasonably be used on multiple architectures the data
* size should be fixed. This should ease the transition between
* 32 bit and 64 bit architectures etc.
*
* The completeness test for the information in this table is:
* - Can all of the hardware be detected?
* - Are the per motherboard constants available?
* - Is there enough to allow a kernel to run that was written before
* a particular motherboard is constructed? (Assuming the kernel
* has drivers for all of the hardware but it does not have
* assumptions on how the hardware is connected together).
*
* With this test it should be straight forward to determine if a
* table entry is required or not. This should remove much of the
* long term compatibility burden as table entries which are
* irrelevant or have been replaced by better alternatives may be
* dropped. Of course it is polite and expedite to include extra
* table entries and be backwards compatible, but it is not required.
*/
/* Since coreboot is usually compiled 32bit, gcc will align 64bit
* types to 32bit boundaries. If the coreboot table is dumped on a
* 64bit system, a uint64_t would be aligned to 64bit boundaries,
* breaking the table format.
*
* lb_uint64 will keep 64bit coreboot table values aligned to 32bit
* to ensure compatibility. They can be accessed with the two functions
* below: unpack_lb64() and pack_lb64()
*
* See also: util/lbtdump/lbtdump.c
*/
struct lb_uint64 {
uint32_t lo;
uint32_t hi;
};
static inline uint64_t unpack_lb64(struct lb_uint64 value)
{
uint64_t result;
result = value.hi;
result = (result << 32) + value.lo;
return result;
}
static inline struct lb_uint64 pack_lb64(uint64_t value)
{
struct lb_uint64 result;
result.lo = (value >> 0) & 0xffffffff;
result.hi = (value >> 32) & 0xffffffff;
return result;
}
struct lb_header
{
uint8_t signature[4]; /* LBIO */
uint32_t header_bytes;
uint32_t header_checksum;
uint32_t table_bytes;
uint32_t table_checksum;
uint32_t table_entries;
};
/* Every entry in the boot environment list will correspond to a boot
* info record. Encoding both type and size. The type is obviously
* so you can tell what it is. The size allows you to skip that
* boot environment record if you don't know what it is. This allows
* forward compatibility with records not yet defined.
*/
struct lb_record {
uint32_t tag; /* tag ID */
uint32_t size; /* size of record (in bytes) */
};
#define LB_TAG_UNUSED 0x0000
#define LB_TAG_MEMORY 0x0001
struct lb_memory_range {
struct lb_uint64 start;
struct lb_uint64 size;
uint32_t type;
#define LB_MEM_RAM 1 /* Memory anyone can use */
#define LB_MEM_RESERVED 2 /* Don't use this memory region */
#define LB_MEM_ACPI 3 /* ACPI Tables */
#define LB_MEM_NVS 4 /* ACPI NVS Memory */
#define LB_MEM_UNUSABLE 5 /* Unusable address space */
#define LB_MEM_VENDOR_RSVD 6 /* Vendor Reserved */
#define LB_MEM_TABLE 16 /* Ram configuration tables are kept in */
};
struct lb_memory {
uint32_t tag;
uint32_t size;
struct lb_memory_range map[0];
};
#define LB_TAG_HWRPB 0x0002
struct lb_hwrpb {
uint32_t tag;
uint32_t size;
uint64_t hwrpb;
};
#define LB_TAG_MAINBOARD 0x0003
struct lb_mainboard {
uint32_t tag;
uint32_t size;
uint8_t vendor_idx;
uint8_t part_number_idx;
uint8_t strings[0];
};
#define LB_TAG_VERSION 0x0004
#define LB_TAG_EXTRA_VERSION 0x0005
#define LB_TAG_BUILD 0x0006
#define LB_TAG_COMPILE_TIME 0x0007
#define LB_TAG_COMPILE_BY 0x0008
#define LB_TAG_COMPILE_HOST 0x0009
#define LB_TAG_COMPILE_DOMAIN 0x000a
#define LB_TAG_COMPILER 0x000b
#define LB_TAG_LINKER 0x000c
#define LB_TAG_ASSEMBLER 0x000d
struct lb_string {
uint32_t tag;
uint32_t size;
uint8_t string[0];
};
#define LB_TAG_VERSION_TIMESTAMP 0x0026
struct lb_timestamp {
uint32_t tag;
uint32_t size;
uint32_t timestamp;
};
/* 0xe is taken by v3 */
#define LB_TAG_SERIAL 0x000f
struct lb_serial {
uint32_t tag;
uint32_t size;
#define LB_SERIAL_TYPE_IO_MAPPED 1
#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
uint32_t type;
uint32_t baseaddr;
uint32_t baud;
uint32_t regwidth;
};
#define LB_TAG_CONSOLE 0x0010
struct lb_console {
uint32_t tag;
uint32_t size;
uint16_t type;
};
#define LB_TAG_CONSOLE_SERIAL8250 0
#define LB_TAG_CONSOLE_VGA 1 // OBSOLETE
#define LB_TAG_CONSOLE_BTEXT 2 // OBSOLETE
#define LB_TAG_CONSOLE_LOGBUF 3 // OBSOLETE
#define LB_TAG_CONSOLE_SROM 4 // OBSOLETE
#define LB_TAG_CONSOLE_EHCI 5
#define LB_TAG_CONSOLE_SERIAL8250MEM 6
#define LB_TAG_FORWARD 0x0011
struct lb_forward {
uint32_t tag;
uint32_t size;
uint64_t forward;
};
#define LB_TAG_FRAMEBUFFER 0x0012
struct lb_framebuffer {
uint32_t tag;
uint32_t size;
uint64_t physical_address;
uint32_t x_resolution;
uint32_t y_resolution;
uint32_t bytes_per_line;
uint8_t bits_per_pixel;
uint8_t red_mask_pos;
uint8_t red_mask_size;
uint8_t green_mask_pos;
uint8_t green_mask_size;
uint8_t blue_mask_pos;
uint8_t blue_mask_size;
uint8_t reserved_mask_pos;
uint8_t reserved_mask_size;
};
#define LB_TAG_GPIO 0x0013
struct lb_gpio {
uint32_t port;
uint32_t polarity;
#define ACTIVE_LOW 0
#define ACTIVE_HIGH 1
uint32_t value;
#define GPIO_MAX_NAME_LENGTH 16
uint8_t name[GPIO_MAX_NAME_LENGTH];
};
struct lb_gpios {
uint32_t tag;
uint32_t size;
uint32_t count;
struct lb_gpio gpios[0];
};
#define LB_TAG_VDAT 0x0015
#define LB_TAG_VBNV 0x0019
#define LB_TAB_VBOOT_HANDOFF 0x0020
#define LB_TAB_DMA 0x0022
#define LB_TAG_RAM_OOPS 0x0023
#define LB_TAG_MTC 0x002b
struct lb_range {
uint32_t tag;
uint32_t size;
uint64_t range_start;
uint32_t range_size;
};
void lb_ramoops(struct lb_header *header);
#define LB_TAG_TIMESTAMPS 0x0016
#define LB_TAG_CBMEM_CONSOLE 0x0017
#define LB_TAG_MRC_CACHE 0x0018
#define LB_TAG_ACPI_GNVS 0x0024
#define LB_TAG_WIFI_CALIBRATION 0x0027
struct lb_cbmem_ref {
uint32_t tag;
uint32_t size;
uint64_t cbmem_addr;
};
#define LB_TAG_X86_ROM_MTRR 0x0021
struct lb_x86_rom_mtrr {
uint32_t tag;
uint32_t size;
/* The variable range MTRR index covering the ROM. */
uint32_t index;
};
#define LB_TAG_BOARD_ID 0x0025
struct lb_board_id {
uint32_t tag;
uint32_t size;
/* Board ID as retrieved from the board revision GPIOs. */
uint32_t board_id;
};
#define LB_TAG_MAC_ADDRS 0x0026
struct mac_address {
uint8_t mac_addr[6];
uint8_t pad[2]; /* Pad it to 8 bytes to keep it simple. */
};
struct lb_macs {
uint32_t tag;
uint32_t size;
uint32_t count;
struct mac_address mac_addrs[0];
};
#define LB_TAG_RAM_CODE 0x0028
struct lb_ram_code {
uint32_t tag;
uint32_t size;
uint32_t ram_code;
};
#define LB_TAG_SPI_FLASH 0x0029
struct lb_spi_flash {
uint32_t tag;
uint32_t size;
uint32_t flash_size;
uint32_t sector_size;
uint32_t erase_cmd;
};
#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
struct lb_boot_media_params {
uint32_t tag;
uint32_t size;
/* offsets are relative to start of boot media */
uint64_t fmap_offset;
uint64_t cbfs_offset;
uint64_t cbfs_size;
uint64_t boot_media_size;
};
#define LB_TAG_SERIALNO 0x002a
#define MAX_SERIALNO_LENGTH 32
/* The following structures are for the cmos definitions table */
#define LB_TAG_CMOS_OPTION_TABLE 200
/* cmos header record */
struct cmos_option_table {
uint32_t tag; /* CMOS definitions table type */
uint32_t size; /* size of the entire table */
uint32_t header_length; /* length of header */
};
/* cmos entry record
This record is variable length. The name field may be
shorter than CMOS_MAX_NAME_LENGTH. The entry may start
anywhere in the byte, but can not span bytes unless it
starts at the beginning of the byte and the length is
fills complete bytes.
*/
#define LB_TAG_OPTION 201
struct cmos_entries {
uint32_t tag; /* entry type */
uint32_t size; /* length of this record */
uint32_t bit; /* starting bit from start of image */
uint32_t length; /* length of field in bits */
uint32_t config; /* e=enumeration, h=hex, r=reserved */
uint32_t config_id; /* a number linking to an enumeration record */
#define CMOS_MAX_NAME_LENGTH 32
uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
variable length int aligned */
};
/* cmos enumerations record
This record is variable length. The text field may be
shorter than CMOS_MAX_TEXT_LENGTH.
*/
#define LB_TAG_OPTION_ENUM 202
struct cmos_enums {
uint32_t tag; /* enumeration type */
uint32_t size; /* length of this record */
uint32_t config_id; /* a number identifying the config id */
uint32_t value; /* the value associated with the text */
#define CMOS_MAX_TEXT_LENGTH 32
uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
variable length int aligned */
};
/* cmos defaults record
This record contains default settings for the cmos ram.
*/
#define LB_TAG_OPTION_DEFAULTS 203
struct cmos_defaults {
uint32_t tag; /* default type */
uint32_t size; /* length of this record */
uint32_t name_length; /* length of the following name field */
uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
#define CMOS_IMAGE_BUFFER_SIZE 256
uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
};
#define LB_TAG_OPTION_CHECKSUM 204
struct cmos_checksum {
uint32_t tag;
uint32_t size;
/* In practice everything is byte aligned, but things are measured
* in bits to be consistent.
*/
uint32_t range_start; /* First bit that is checksummed (byte aligned) */
uint32_t range_end; /* Last bit that is checksummed (byte aligned) */
uint32_t location; /* First bit of the checksum (byte aligned) */
uint32_t type; /* Checksum algorithm that is used */
#define CHECKSUM_NONE 0
#define CHECKSUM_PCBIOS 1
};
#endif

0
src/include/fmap_serialized.h → src/commonlib/include/commonlib/fmap_serialized.h
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51
src/commonlib/include/commonlib/helpers.h Normal file
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@ -0,0 +1,51 @@
#ifndef COMMONLIB_HELPERS_H
#define COMMONLIB_HELPERS_H
/* This file is for helpers for both coreboot firmware and its utilities. */
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1UL)
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
#define ALIGN_UP(x,a) ALIGN((x),(a))
#define ALIGN_DOWN(x,a) ((x) & ~((typeof(x))(a)-1UL))
#define IS_ALIGNED(x,a) (((x) & ((typeof(x))(a)-1UL)) == 0)
#define MIN(a,b) ((a) < (b) ? (a) : (b))
#define MAX(a,b) ((a) > (b) ? (a) : (b))
#define ABS(a) (((a) < 0) ? (-(a)) : (a))
#define CEIL_DIV(a, b) (((a) + (b) - 1) / (b))
#define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0)
/* Standard units. */
#define KiB (1<<10)
#define MiB (1<<20)
#define GiB (1<<30)
/* Could we ever run into this one? I hope we get this much memory! */
#define TiB (1<<40)
#define KHz (1000)
#define MHz (1000 * KHz)
#define GHz (1000 * MHz)
#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
#if !defined(__clang__)
#define check_member(structure, member, offset) _Static_assert( \
offsetof(struct structure, member) == offset, \
"`struct " #structure "` offset for `" #member "` is not " #offset )
#else
#define check_member(structure, member, offset)
#endif
/**
* container_of - cast a member of a structure out to the containing structure
* @param ptr: the pointer to the member.
* @param type: the type of the container struct this is embedded in.
* @param member: the name of the member within the struct.
*
*/
#define container_of(ptr, type, member) ({ \
const typeof( ((type *)0)->member ) *__mptr = (ptr); \
(type *)( (char *)__mptr - offsetof(type,member) );})
#endif /* COMMONLIB_HELPERS_H */

0
src/include/console/loglevel.h → src/commonlib/include/commonlib/loglevel.h
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0
src/include/mem_pool.h → src/commonlib/include/commonlib/mem_pool.h
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2
src/include/region.h → src/commonlib/include/commonlib/region.h
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@ -22,7 +22,7 @@
#include <stdint.h>
#include <stddef.h>
#include <mem_pool.h>
#include <commonlib/mem_pool.h>
/*
* Region support.

0
src/include/rmodule-defs.h → src/commonlib/include/commonlib/rmodule-defs.h
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92
src/commonlib/include/commonlib/timestamp_serialized.h Normal file
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@ -0,0 +1,92 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#ifndef __TIMESTAMP_SERIALIZED_H__
#define __TIMESTAMP_SERIALIZED_H__
#include <stdint.h>
struct timestamp_entry {
uint32_t entry_id;
uint64_t entry_stamp;
} __attribute__((packed));
struct timestamp_table {
uint64_t base_time;
uint16_t max_entries;
uint16_t tick_freq_mhz;
uint32_t num_entries;
struct timestamp_entry entries[0]; /* Variable number of entries */
} __attribute__((packed));
enum timestamp_id {
TS_START_ROMSTAGE = 1,
TS_BEFORE_INITRAM = 2,
TS_AFTER_INITRAM = 3,
TS_END_ROMSTAGE = 4,
TS_START_VBOOT = 5,
TS_END_VBOOT = 6,
TS_START_COPYRAM = 8,
TS_END_COPYRAM = 9,
TS_START_RAMSTAGE = 10,
TS_START_BOOTBLOCK = 11,
TS_END_BOOTBLOCK = 12,
TS_START_COPYROM = 13,
TS_END_COPYROM = 14,
TS_START_ULZMA = 15,
TS_END_ULZMA = 16,
TS_DEVICE_ENUMERATE = 30,
TS_DEVICE_CONFIGURE = 40,
TS_DEVICE_ENABLE = 50,
TS_DEVICE_INITIALIZE = 60,
TS_DEVICE_DONE = 70,
TS_CBMEM_POST = 75,
TS_WRITE_TABLES = 80,
TS_LOAD_PAYLOAD = 90,
TS_ACPI_WAKE_JUMP = 98,
TS_SELFBOOT_JUMP = 99,
/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
TS_START_COPYVER = 501,
TS_END_COPYVER = 502,
TS_START_TPMINIT = 503,
TS_END_TPMINIT = 504,
TS_START_VERIFY_SLOT = 505,
TS_END_VERIFY_SLOT = 506,
TS_START_HASH_BODY = 507,
TS_DONE_LOADING = 508,
TS_DONE_HASHING = 509,
TS_END_HASH_BODY = 510,
/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
TS_FSP_MEMORY_INIT_START = 950,
TS_FSP_MEMORY_INIT_END = 951,
TS_FSP_TEMP_RAM_EXIT_START = 952,
TS_FSP_TEMP_RAM_EXIT_END = 953,
TS_FSP_SILICON_INIT_START = 954,
TS_FSP_SILICON_INIT_END = 955,
TS_FSP_BEFORE_ENUMERATE = 956,
TS_FSP_AFTER_ENUMERATE = 957,
TS_FSP_BEFORE_FINALIZE = 958,
TS_FSP_AFTER_FINALIZE = 959,
/* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
};
#endif

2
src/lib/mem_pool.c → src/commonlib/mem_pool.c
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@ -17,7 +17,7 @@
* Foundation, Inc.
*/
#include <mem_pool.h>
#include <commonlib/mem_pool.h>
#include <stdlib.h>
void *mem_pool_alloc(struct mem_pool *mp, size_t sz)

2
src/lib/region.c → src/commonlib/region.c
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@ -17,7 +17,7 @@
* Foundation, Inc.
*/
#include <region.h>
#include <commonlib/region.h>
#include <string.h>
static inline size_t region_end(const struct region *r)

2
src/drivers/intel/fsp1_1/include/fsp/util.h
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@ -26,7 +26,7 @@
#include <fsp/soc_binding.h>
#include <fsp/gop.h>
#include <program_loading.h>
#include <region.h>
#include <commonlib/region.h>
/* find_fsp() should only be called from assembly code. */
FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);

2
src/include/assets.h
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@ -19,7 +19,7 @@
#ifndef ASSETS_H
#define ASSETS_H
#include <region.h>
#include <commonlib/region.h>
/* An asset represents data used to boot the system. It can be found within
* CBFS or some other mechanism. While CBFS can be a source of an asset, note

384
src/include/boot/coreboot_tables.h
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@ -1,389 +1,7 @@
#ifndef COREBOOT_TABLES_H
#define COREBOOT_TABLES_H
#include <stdint.h>
/* The coreboot table information is for conveying information
* from the firmware to the loaded OS image. Primarily this
* is expected to be information that cannot be discovered by
* other means, such as querying the hardware directly.
*
* All of the information should be Position Independent Data.
* That is it should be safe to relocated any of the information
* without it's meaning/correctness changing. For table that
* can reasonably be used on multiple architectures the data
* size should be fixed. This should ease the transition between
* 32 bit and 64 bit architectures etc.
*
* The completeness test for the information in this table is:
* - Can all of the hardware be detected?
* - Are the per motherboard constants available?
* - Is there enough to allow a kernel to run that was written before
* a particular motherboard is constructed? (Assuming the kernel
* has drivers for all of the hardware but it does not have
* assumptions on how the hardware is connected together).
*
* With this test it should be straight forward to determine if a
* table entry is required or not. This should remove much of the
* long term compatibility burden as table entries which are
* irrelevant or have been replaced by better alternatives may be
* dropped. Of course it is polite and expedite to include extra
* table entries and be backwards compatible, but it is not required.
*/
/* Since coreboot is usually compiled 32bit, gcc will align 64bit
* types to 32bit boundaries. If the coreboot table is dumped on a
* 64bit system, a uint64_t would be aligned to 64bit boundaries,
* breaking the table format.
*
* lb_uint64 will keep 64bit coreboot table values aligned to 32bit
* to ensure compatibility. They can be accessed with the two functions
* below: unpack_lb64() and pack_lb64()
*
* See also: util/lbtdump/lbtdump.c
*/
struct lb_uint64 {
uint32_t lo;
uint32_t hi;
};
static inline uint64_t unpack_lb64(struct lb_uint64 value)
{
uint64_t result;
result = value.hi;
result = (result << 32) + value.lo;
return result;
}
static inline struct lb_uint64 pack_lb64(uint64_t value)
{
struct lb_uint64 result;
result.lo = (value >> 0) & 0xffffffff;
result.hi = (value >> 32) & 0xffffffff;
return result;
}
struct lb_header
{
uint8_t signature[4]; /* LBIO */
uint32_t header_bytes;
uint32_t header_checksum;
uint32_t table_bytes;
uint32_t table_checksum;
uint32_t table_entries;
};
/* Every entry in the boot environment list will correspond to a boot
* info record. Encoding both type and size. The type is obviously
* so you can tell what it is. The size allows you to skip that
* boot environment record if you don't know what it is. This allows
* forward compatibility with records not yet defined.
*/
struct lb_record {
uint32_t tag; /* tag ID */
uint32_t size; /* size of record (in bytes) */
};
#define LB_TAG_UNUSED 0x0000
#define LB_TAG_MEMORY 0x0001
struct lb_memory_range {
struct lb_uint64 start;
struct lb_uint64 size;
uint32_t type;
#define LB_MEM_RAM 1 /* Memory anyone can use */
#define LB_MEM_RESERVED 2 /* Don't use this memory region */
#define LB_MEM_ACPI 3 /* ACPI Tables */
#define LB_MEM_NVS 4 /* ACPI NVS Memory */
#define LB_MEM_UNUSABLE 5 /* Unusable address space */
#define LB_MEM_VENDOR_RSVD 6 /* Vendor Reserved */
#define LB_MEM_TABLE 16 /* Ram configuration tables are kept in */
};
struct lb_memory {
uint32_t tag;
uint32_t size;
struct lb_memory_range map[0];
};
#define LB_TAG_HWRPB 0x0002
struct lb_hwrpb {
uint32_t tag;
uint32_t size;
uint64_t hwrpb;
};
#define LB_TAG_MAINBOARD 0x0003
struct lb_mainboard {
uint32_t tag;
uint32_t size;
uint8_t vendor_idx;
uint8_t part_number_idx;
uint8_t strings[0];
};
#define LB_TAG_VERSION 0x0004
#define LB_TAG_EXTRA_VERSION 0x0005
#define LB_TAG_BUILD 0x0006
#define LB_TAG_COMPILE_TIME 0x0007
#define LB_TAG_COMPILE_BY 0x0008
#define LB_TAG_COMPILE_HOST 0x0009
#define LB_TAG_COMPILE_DOMAIN 0x000a
#define LB_TAG_COMPILER 0x000b
#define LB_TAG_LINKER 0x000c
#define LB_TAG_ASSEMBLER 0x000d
struct lb_string {
uint32_t tag;
uint32_t size;
uint8_t string[0];
};
#define LB_TAG_VERSION_TIMESTAMP 0x0026
struct lb_timestamp {
uint32_t tag;
uint32_t size;
uint32_t timestamp;
};
/* 0xe is taken by v3 */
#define LB_TAG_SERIAL 0x000f
struct lb_serial {
uint32_t tag;
uint32_t size;
#define LB_SERIAL_TYPE_IO_MAPPED 1
#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
uint32_t type;
uint32_t baseaddr;
uint32_t baud;
uint32_t regwidth;
};
#define LB_TAG_CONSOLE 0x0010
struct lb_console {
uint32_t tag;
uint32_t size;
uint16_t type;
};
#define LB_TAG_CONSOLE_SERIAL8250 0
#define LB_TAG_CONSOLE_VGA 1 // OBSOLETE
#define LB_TAG_CONSOLE_BTEXT 2 // OBSOLETE
#define LB_TAG_CONSOLE_LOGBUF 3 // OBSOLETE
#define LB_TAG_CONSOLE_SROM 4 // OBSOLETE
#define LB_TAG_CONSOLE_EHCI 5
#define LB_TAG_CONSOLE_SERIAL8250MEM 6
#define LB_TAG_FORWARD 0x0011
struct lb_forward {
uint32_t tag;
uint32_t size;
uint64_t forward;
};
#define LB_TAG_FRAMEBUFFER 0x0012
struct lb_framebuffer {
uint32_t tag;
uint32_t size;
uint64_t physical_address;
uint32_t x_resolution;
uint32_t y_resolution;
uint32_t bytes_per_line;
uint8_t bits_per_pixel;
uint8_t red_mask_pos;
uint8_t red_mask_size;
uint8_t green_mask_pos;
uint8_t green_mask_size;
uint8_t blue_mask_pos;
uint8_t blue_mask_size;
uint8_t reserved_mask_pos;
uint8_t reserved_mask_size;
};
#define LB_TAG_GPIO 0x0013
struct lb_gpio {
uint32_t port;
uint32_t polarity;
#define ACTIVE_LOW 0
#define ACTIVE_HIGH 1
uint32_t value;
#define GPIO_MAX_NAME_LENGTH 16
uint8_t name[GPIO_MAX_NAME_LENGTH];
};
struct lb_gpios {
uint32_t tag;
uint32_t size;
uint32_t count;
struct lb_gpio gpios[0];
};
#define LB_TAG_VDAT 0x0015
#define LB_TAG_VBNV 0x0019
#define LB_TAB_VBOOT_HANDOFF 0x0020
#define LB_TAB_DMA 0x0022
#define LB_TAG_RAM_OOPS 0x0023
#define LB_TAG_MTC 0x002b
struct lb_range {
uint32_t tag;
uint32_t size;
uint64_t range_start;
uint32_t range_size;
};
void lb_ramoops(struct lb_header *header);
#define LB_TAG_TIMESTAMPS 0x0016
#define LB_TAG_CBMEM_CONSOLE 0x0017
#define LB_TAG_MRC_CACHE 0x0018
#define LB_TAG_ACPI_GNVS 0x0024
#define LB_TAG_WIFI_CALIBRATION 0x0027
struct lb_cbmem_ref {
uint32_t tag;
uint32_t size;
uint64_t cbmem_addr;
};
#define LB_TAG_X86_ROM_MTRR 0x0021
struct lb_x86_rom_mtrr {
uint32_t tag;
uint32_t size;
/* The variable range MTRR index covering the ROM. */
uint32_t index;
};
#define LB_TAG_BOARD_ID 0x0025
struct lb_board_id {
uint32_t tag;
uint32_t size;
/* Board ID as retrieved from the board revision GPIOs. */
uint32_t board_id;
};
#define LB_TAG_MAC_ADDRS 0x0026
struct mac_address {
uint8_t mac_addr[6];
uint8_t pad[2]; /* Pad it to 8 bytes to keep it simple. */
};
struct lb_macs {
uint32_t tag;
uint32_t size;
uint32_t count;
struct mac_address mac_addrs[0];
};
#define LB_TAG_RAM_CODE 0x0028
struct lb_ram_code {
uint32_t tag;
uint32_t size;
uint32_t ram_code;
};
#define LB_TAG_SPI_FLASH 0x0029
struct lb_spi_flash {
uint32_t tag;
uint32_t size;
uint32_t flash_size;
uint32_t sector_size;
uint32_t erase_cmd;
};
#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
struct lb_boot_media_params {
uint32_t tag;
uint32_t size;
/* offsets are relative to start of boot media */
uint64_t fmap_offset;
uint64_t cbfs_offset;
uint64_t cbfs_size;
uint64_t boot_media_size;
};
#define LB_TAG_SERIALNO 0x002a
#define MAX_SERIALNO_LENGTH 32
/* The following structures are for the cmos definitions table */
#define LB_TAG_CMOS_OPTION_TABLE 200
/* cmos header record */
struct cmos_option_table {
uint32_t tag; /* CMOS definitions table type */
uint32_t size; /* size of the entire table */
uint32_t header_length; /* length of header */
};
/* cmos entry record
This record is variable length. The name field may be
shorter than CMOS_MAX_NAME_LENGTH. The entry may start
anywhere in the byte, but can not span bytes unless it
starts at the beginning of the byte and the length is
fills complete bytes.
*/
#define LB_TAG_OPTION 201
struct cmos_entries {
uint32_t tag; /* entry type */
uint32_t size; /* length of this record */
uint32_t bit; /* starting bit from start of image */
uint32_t length; /* length of field in bits */
uint32_t config; /* e=enumeration, h=hex, r=reserved */
uint32_t config_id; /* a number linking to an enumeration record */
#define CMOS_MAX_NAME_LENGTH 32
uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
variable length int aligned */
};
/* cmos enumerations record
This record is variable length. The text field may be
shorter than CMOS_MAX_TEXT_LENGTH.
*/
#define LB_TAG_OPTION_ENUM 202
struct cmos_enums {
uint32_t tag; /* enumeration type */
uint32_t size; /* length of this record */
uint32_t config_id; /* a number identifying the config id */
uint32_t value; /* the value associated with the text */
#define CMOS_MAX_TEXT_LENGTH 32
uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
variable length int aligned */
};
/* cmos defaults record
This record contains default settings for the cmos ram.
*/
#define LB_TAG_OPTION_DEFAULTS 203
struct cmos_defaults {
uint32_t tag; /* default type */
uint32_t size; /* length of this record */
uint32_t name_length; /* length of the following name field */
uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
#define CMOS_IMAGE_BUFFER_SIZE 256
uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
};
#define LB_TAG_OPTION_CHECKSUM 204
struct cmos_checksum {
uint32_t tag;
uint32_t size;
/* In practice everything is byte aligned, but things are measured
* in bits to be consistent.
*/
uint32_t range_start; /* First bit that is checksummed (byte aligned) */
uint32_t range_end; /* Last bit that is checksummed (byte aligned) */
uint32_t location; /* First bit of the checksum (byte aligned) */
uint32_t type; /* Checksum algorithm that is used */
#define CHECKSUM_NONE 0
#define CHECKSUM_PCBIOS 1
};
#include <commonlib/coreboot_tables.h>
/* function prototypes for building the coreboot table */
unsigned long write_coreboot_table(

2
src/include/boot_device.h
View File

@ -20,7 +20,7 @@
#ifndef _BOOT_DEVICE_H_
#define _BOOT_DEVICE_H_
#include <region.h>
#include <commonlib/region.h>
/* Return the region_device for the read-only boot device. */
const struct region_device *boot_device_ro(void);

4
src/include/cbfs.h
View File

@ -20,9 +20,9 @@
#ifndef _CBFS_H_
#define _CBFS_H_
#include <cbfs_serialized.h>
#include <commonlib/cbfs_serialized.h>
#include <commonlib/region.h>
#include <program_loading.h>
#include <region.h>
/*
* CBFS operations consist of the following concepts:

2
src/include/cbmem.h
View File

@ -21,7 +21,7 @@
#ifndef _CBMEM_H_
#define _CBMEM_H_
#include <cbmem_id.h>
#include <commonlib/cbmem_id.h>
#include <rules.h>
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \

2
src/include/console/console.h
View File

@ -23,7 +23,7 @@
#include <stdint.h>
#include <rules.h>
#include <console/post_codes.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#ifndef __ROMCC__
struct console_driver {

2
src/include/console/early_print.h
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@ -24,7 +24,7 @@
#include <console/console.h>
#include <console/streams.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
/* While in romstage, console loglevel is built-time constant.
* With ROMCC we inline this test with help from preprocessor.

4
src/include/fmap.h
View File

@ -20,8 +20,8 @@
#ifndef _FMAP_H_
#define _FMAP_H_
#include <region.h>
#include <fmap_serialized.h>
#include <commonlib/region.h>
#include <commonlib/fmap_serialized.h>
/* Locate the fmap directory. Return 0 on success, < 0 on error. */
int find_fmap_directory(struct region_device *fmrd);

2
src/include/rmodule.h
View File

@ -22,7 +22,7 @@
#include <stdint.h>
#include <stddef.h>
#include <string.h>
#include <rmodule-defs.h>
#include <commonlib/rmodule-defs.h>
enum {
RMODULE_TYPE_SMM,

34
src/include/stddef.h
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@ -1,6 +1,8 @@
#ifndef STDDEF_H
#define STDDEF_H
#include <commonlib/helpers.h>
typedef long ptrdiff_t;
#ifndef __SIZE_TYPE__
#define __SIZE_TYPE__ unsigned long
@ -19,38 +21,6 @@ typedef unsigned int wint_t;
#define NULL ((void *)0)
/* Standard units. */
#define KiB (1<<10)
#define MiB (1<<20)
#define GiB (1<<30)
/* Could we ever run into this one? I hope we get this much memory! */
#define TiB (1<<40)
#define KHz (1000)
#define MHz (1000 * KHz)
#define GHz (1000 * MHz)
#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
#if !defined(__clang__)
#define check_member(structure, member, offset) _Static_assert( \
offsetof(struct structure, member) == offset, \
"`struct " #structure "` offset for `" #member "` is not " #offset )
#else
#define check_member(structure, member, offset)
#endif
/**
* container_of - cast a member of a structure out to the containing structure
* @param ptr: the pointer to the member.
* @param type: the type of the container struct this is embedded in.
* @param member: the name of the member within the struct.
*
*/
#define container_of(ptr, type, member) ({ \
const typeof( ((type *)0)->member ) *__mptr = (ptr); \
(type *)( (char *)__mptr - offsetof(type,member) );})
#ifdef __PRE_RAM__
#define ROMSTAGE_CONST const
#else

14
src/include/stdlib.h
View File

@ -3,20 +3,6 @@
#include <stddef.h>
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1UL)
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
#define ALIGN_UP(x,a) ALIGN((x),(a))
#define ALIGN_DOWN(x,a) ((x) & ~((typeof(x))(a)-1UL))
#define IS_ALIGNED(x,a) (((x) & ((typeof(x))(a)-1UL)) == 0)
#define MIN(a,b) ((a) < (b) ? (a) : (b))
#define MAX(a,b) ((a) > (b) ? (a) : (b))
#define ABS(a) (((a) < 0) ? (-(a)) : (a))
#define CEIL_DIV(a, b) (((a) + (b) - 1) / (b))
#define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0)
#define min(a,b) MIN((a),(b))
#define max(a,b) MAX((a),(b))

69
src/include/timestamp.h
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@ -20,74 +20,7 @@
#ifndef __TIMESTAMP_H__
#define __TIMESTAMP_H__
#include <stdint.h>
struct timestamp_entry {
uint32_t entry_id;
uint64_t entry_stamp;
} __attribute__((packed));
struct timestamp_table {
uint64_t base_time;
uint16_t max_entries;
uint16_t tick_freq_mhz;
uint32_t num_entries;
struct timestamp_entry entries[0]; /* Variable number of entries */
} __attribute__((packed));
enum timestamp_id {
TS_START_ROMSTAGE = 1,
TS_BEFORE_INITRAM = 2,
TS_AFTER_INITRAM = 3,
TS_END_ROMSTAGE = 4,
TS_START_VBOOT = 5,
TS_END_VBOOT = 6,
TS_START_COPYRAM = 8,
TS_END_COPYRAM = 9,
TS_START_RAMSTAGE = 10,
TS_START_BOOTBLOCK = 11,
TS_END_BOOTBLOCK = 12,
TS_START_COPYROM = 13,
TS_END_COPYROM = 14,
TS_START_ULZMA = 15,
TS_END_ULZMA = 16,
TS_DEVICE_ENUMERATE = 30,
TS_DEVICE_CONFIGURE = 40,
TS_DEVICE_ENABLE = 50,
TS_DEVICE_INITIALIZE = 60,
TS_DEVICE_DONE = 70,
TS_CBMEM_POST = 75,
TS_WRITE_TABLES = 80,
TS_LOAD_PAYLOAD = 90,
TS_ACPI_WAKE_JUMP = 98,
TS_SELFBOOT_JUMP = 99,
/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
TS_START_COPYVER = 501,
TS_END_COPYVER = 502,
TS_START_TPMINIT = 503,
TS_END_TPMINIT = 504,
TS_START_VERIFY_SLOT = 505,
TS_END_VERIFY_SLOT = 506,
TS_START_HASH_BODY = 507,
TS_DONE_LOADING = 508,
TS_DONE_HASHING = 509,
TS_END_HASH_BODY = 510,
/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
TS_FSP_MEMORY_INIT_START = 950,
TS_FSP_MEMORY_INIT_END = 951,
TS_FSP_TEMP_RAM_EXIT_START = 952,
TS_FSP_TEMP_RAM_EXIT_END = 953,
TS_FSP_SILICON_INIT_START = 954,
TS_FSP_SILICON_INIT_END = 955,
TS_FSP_BEFORE_ENUMERATE = 956,
TS_FSP_AFTER_ENUMERATE = 957,
TS_FSP_BEFORE_FINALIZE = 958,
TS_FSP_AFTER_FINALIZE = 959,
/* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
};
#include <commonlib/timestamp_serialized.h>
#if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__))
/*

9
src/lib/Makefile.inc
View File

@ -33,8 +33,6 @@ bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
bootblock-$(CONFIG_I2C_TPM) += delay.c
bootblock-y += memchr.c
bootblock-y += memcmp.c
bootblock-y += mem_pool.c
bootblock-y += region.c
bootblock-y += boot_device.c
bootblock-y += fmap.c
@ -49,7 +47,6 @@ verstage-y += cbfs_boot_props.c
verstage-y += libgcc.c
verstage-y += memcmp.c
verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
verstage-y += region.c
verstage-y += boot_device.c
verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
@ -62,7 +59,6 @@ endif
verstage-$(CONFIG_GENERIC_UDELAY) += timer.c
verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
verstage-y += mem_pool.c
romstage-y += assets.c
romstage-y += prog_loaders.c
@ -155,15 +151,10 @@ ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
endif
romstage-y += mem_pool.c
ramstage-y += mem_pool.c
romstage-y += region.c
ramstage-y += region.c
romstage-y += boot_device.c
ramstage-y += boot_device.c
smm-y += region.c
smm-y += boot_device.c
smm-y += fmap.c
smm-y += cbfs.c memcmp.c

2
src/lib/cbfs_boot_props.c
View File

@ -21,7 +21,7 @@
#include <cbfs.h>
#include <console/console.h>
#include <endian.h>
#include <region.h>
#include <commonlib/region.h>
/* This function is marked as weak to allow a particular platform to
* override the logic. This implementation should work for most devices. */

2
src/lib/fmap.c
View File

@ -20,7 +20,7 @@
#include <boot_device.h>
#include <console/console.h>
#include <fmap.h>
#include <fmap_serialized.h>
#include <commonlib/fmap_serialized.h>
#include <stddef.h>
#include <string.h>

2
src/mainboard/advansus/a785e-i/romstage.c
View File

@ -40,7 +40,7 @@
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>

2
src/mainboard/amd/bimini_fam10/romstage.c
View File

@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"

2
src/mainboard/amd/dinar/romstage.c
View File

@ -27,7 +27,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>

2
src/mainboard/amd/inagua/romstage.c
View File

@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>

2
src/mainboard/amd/lamar/romstage.c
View File

@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>

2
src/mainboard/amd/mahogany_fam10/romstage.c
View File

@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>

2
src/mainboard/amd/olivehill/romstage.c
View File

@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>

2
src/mainboard/amd/olivehillplus/romstage.c
View File

@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>

2
src/mainboard/amd/parmer/romstage.c
View File

@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>

2
src/mainboard/amd/persimmon/romstage.c
View File

@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>

2
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
View File

@ -42,7 +42,7 @@
#include <spd.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdfam10/debug.c"
#include <superio/winbond/common/winbond.h>

2
src/mainboard/amd/south_station/romstage.c
View File

@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>

2
src/mainboard/amd/thatcher/romstage.c
View File

@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>

2
src/mainboard/amd/tilapia_fam10/romstage.c
View File

@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>

2
src/mainboard/amd/torpedo/romstage.c
View File

@ -26,7 +26,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>

2
src/mainboard/amd/union_station/romstage.c
View File

@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>

2
src/mainboard/asrock/e350m1/romstage.c
View File

@ -27,7 +27,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>

2
src/mainboard/asrock/imb-a180/romstage.c
View File

@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>

2
src/mainboard/asus/m4a78-em/romstage.c
View File

@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>

2
src/mainboard/asus/m4a785-m/romstage.c
View File

@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>

2
src/mainboard/asus/m5a88-v/romstage.c
View File

@ -40,7 +40,7 @@
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8721f/it8721f.h>

2
src/mainboard/avalue/eax-785e/romstage.c
View File

@ -40,7 +40,7 @@
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>

2
src/mainboard/bap/ode_e20XX/romstage.c
View File

@ -30,7 +30,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>

2
src/mainboard/biostar/am1ml/romstage.c
View File

@ -29,7 +29,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>

2
src/mainboard/gigabyte/ma785gm/romstage.c
View File

@ -36,7 +36,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>

2
src/mainboard/gigabyte/ma785gmt/romstage.c
View File

@ -36,7 +36,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>

2
src/mainboard/gigabyte/ma78gm/romstage.c
View File

@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>

2
src/mainboard/gizmosphere/gizmo/romstage.c
View File

@ -29,7 +29,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>

2
src/mainboard/gizmosphere/gizmo2/romstage.c
View File

@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>

2
src/mainboard/google/peach_pit/romstage.c
View File

@ -24,11 +24,11 @@
#include <boot_device.h>
#include <cbfs.h>
#include <cbmem.h>
#include <commonlib/region.h>
#include <console/console.h>
#include <device/i2c.h>
#include <drivers/maxim/max77802/max77802.h>
#include <program_loading.h>
#include <region.h>
#include <soc/clk.h>
#include <soc/cpu.h>
#include <soc/dmc.h>

2
src/mainboard/hp/abm/romstage.c
View File

@ -29,7 +29,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>

2
src/mainboard/iei/kino-780am2-fam10/romstage.c
View File

@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f71859/f71859.h>

2
src/mainboard/jetway/nf81-t56n-lf/romstage.c
View File

@ -35,7 +35,7 @@
#include <stdint.h>
#include <string.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/amd/mtrr.h>

2
src/mainboard/jetway/pa78vm5/romstage.c
View File

@ -41,7 +41,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f71863fg/f71863fg.h>

2
src/mainboard/lippert/frontrunner-af/romstage.c
View File

@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>

2
src/mainboard/lippert/toucan-af/romstage.c
View File

@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>

2
src/mainboard/pcengines/apu1/romstage.c
View File

@ -30,7 +30,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>

2
src/mainboard/supermicro/h8scm_fam10/romstage.c
View File

@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"

2
src/soc/intel/broadwell/include/soc/me.h
View File

@ -20,7 +20,7 @@
#ifndef _BROADWELL_ME_H_
#define _BROADWELL_ME_H_
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#define ME_RETRY 100000 /* 1 second */
#define ME_DELAY 10 /* 10 us */

2
src/southbridge/amd/cimx/sb700/Platform.h
View File

@ -24,7 +24,7 @@
#include <cpu/amd/common/cbtypes.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#ifdef NULL
#undef NULL
#endif

2
src/southbridge/amd/cimx/sb700/early.c
View File

@ -24,7 +24,7 @@
#include "sb_cimx.h"
#include "sb700_cfg.h" /*sb700_cimx_config*/
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include "smbus.h"
/**

2
src/southbridge/amd/cimx/sb900/early.c
View File

@ -26,7 +26,7 @@
#include "SbPlatform.h"
#include "sb_cimx.h"
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#include "smbus.h"
/**

2
src/vendorcode/amd/agesa/common/Porting.h
View File

@ -255,7 +255,7 @@
#include <assert.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#ifndef NULL
#define NULL (void *)0

2
src/vendorcode/amd/pi/00630F01/Porting.h
View File

@ -272,7 +272,7 @@
#include <assert.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#ifndef NULL
#define NULL ((void *)0)

2
src/vendorcode/amd/pi/00660F01/Porting.h
View File

@ -259,7 +259,7 @@
#include <assert.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#ifndef NULL
#define NULL (void *)0

2
src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
View File

@ -50,7 +50,7 @@
#include "amdlib.h"
#include "cbfs.h"
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
// TODO Add a kconfig option to name the AGESA ROM file in CBFS
#define CONFIG_CBFS_AGESA_NAME "AGESA"

2
src/vendorcode/amd/pi/00730F01/Porting.h
View File

@ -280,7 +280,7 @@
#include <assert.h>
#include <config.h>
#include <console/console.h>
#include <console/loglevel.h>
#include <commonlib/loglevel.h>
#ifndef NULL
#define NULL ((void *)0)

1
src/vendorcode/amd/pi/Makefile.inc
View File

@ -61,6 +61,7 @@ AGESA_INC += -I$(src)/southbridge/amd/pi/hudson
AGESA_INC += -I$(src)/arch/x86/include
AGESA_INC += -I$(src)/include
AGESA_INC += -I$(src)/commonlib/include
AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing
CFLAGS_x86_32 += $(AGESA_CFLAGS)

2
src/vendorcode/google/chromeos/vboot_common.h
View File

@ -20,7 +20,7 @@
#define VBOOT_COMMON_H
#include <stdint.h>
#include <region.h>
#include <commonlib/region.h>
/* The FW areas consist of multiple components. At the beginning of
* each area is the number of total compoments as well as the size and

1
util/cbfstool/Makefile.inc
View File

@ -50,6 +50,7 @@ TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap
TOOLCPPFLAGS += -I$(top)/util/cbfstool
TOOLCPPFLAGS += -I$(objutil)/cbfstool
TOOLCPPFLAGS += -I$(src)/commonlib/include
TOOLLDFLAGS ?=
ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)

2
util/cbfstool/rmodule.c
View File

@ -22,7 +22,7 @@
#include "elfparsing.h"
#include "rmodule.h"
#include "../../src/include/rmodule-defs.h"
#include <commonlib/rmodule-defs.h>
/*
* Architecture specific support operations.

2
util/cbmem/Makefile
View File

@ -22,7 +22,7 @@ ROOT = ../../src
CC ?= $(CROSS_COMPILE)gcc
CFLAGS ?= -O2
CFLAGS += -Wall -Werror
CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86
CPPFLAGS += -I $(ROOT)/commonlib/include
OBJS = $(PROGRAM).o

9
util/cbmem/cbmem.c
View File

@ -34,6 +34,9 @@
#include <sys/mman.h>
#include <libgen.h>
#include <assert.h>
#include <commonlib/cbmem_id.h>
#include <commonlib/timestamp_serialized.h>
#include <commonlib/coreboot_tables.h>
#ifdef __OpenBSD__
#include <sys/param.h>
@ -42,18 +45,12 @@
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
#define MAP_BYTES (1024*1024)
#define IS_ENABLED(x) (defined (x) && (x))
#include "boot/coreboot_tables.h"
typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
typedef uint64_t u64;
#include "cbmem_id.h"
#include "timestamp.h"
#define CBMEM_VERSION "1.1"
/* verbose output? */