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soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S 

According to Intel DOC #630603 P2SB BAR must be at 0xe0000000 for
PCH-S.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie6db3f7108ff1edf62c94876412adfc6421034d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Michał Żygowski 2022-04-07 15:09:19 +02:00
parent f3cc03b137
commit dccfb8a215
1 changed files with 1 additions and 0 deletions
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src/soc/intel/alderlake/Kconfig
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@ -251,6 +251,7 @@ config SMM_RESERVED_SIZE
config PCR_BASE_ADDRESS config PCR_BASE_ADDRESS
hex hex
default 0xe0000000 if SOC_INTEL_ALDERLAKE_PCH_S
default 0xfd000000 default 0xfd000000
help help
This option allows you to select MMIO Base Address of sideband bus. This option allows you to select MMIO Base Address of sideband bus.