nb/intel/sandybridge: Improve CAS freq selection
The previous code seemed weird and tried to check if its selected value is supported three times. This also lower the clock if a selected frequency does not result in a supported CAS number. Change-Id: I97244bc3940813c5a5fcbd770d71cca76d21fcae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Arthur Heymans
parent
f6934f5c6c
commit
dcd3cef874
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@ -39,6 +39,8 @@
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* These values are in 1/256 ns units.
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* @{
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*/
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#define NS2MHZ_DIV256 1000 << 8
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#define TCK_1333MHZ 192
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#define TCK_1200MHZ 212
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#define TCK_1100MHZ 232
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@ -136,16 +136,65 @@ static u32 get_COMP2(u32 tCK)
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return frq_comp2_map[get_FRQ(tCK) - 3];
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}
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static void dram_timing(ramctr_timing * ctrl)
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static void snb_normalize_tclk(u32 *tclk)
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{
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if (*tclk <= TCK_1066MHZ) {
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*tclk = TCK_1066MHZ;
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} else if (*tclk <= TCK_933MHZ) {
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*tclk = TCK_933MHZ;
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} else if (*tclk <= TCK_800MHZ) {
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*tclk = TCK_800MHZ;
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} else if (*tclk <= TCK_666MHZ) {
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*tclk = TCK_666MHZ;
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} else if (*tclk <= TCK_533MHZ) {
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*tclk = TCK_533MHZ;
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} else if (*tclk <= TCK_400MHZ) {
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*tclk = TCK_400MHZ;
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} else {
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*tclk = 0;
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}
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}
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static void find_cas_tck(ramctr_timing *ctrl)
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{
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u8 val;
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u32 val32;
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/* Find CAS latency */
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while (1) {
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/* Normalising tCK before computing clock could potentially
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* results in lower selected CAS, which is desired.
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*/
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snb_normalize_tclk(&(ctrl->tCK));
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if (!(ctrl->tCK))
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die("Couldn't find compatible clock / CAS settings\n");
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val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK);
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printk(BIOS_DEBUG, "Trying CAS %u, tCK %u.\n", val, ctrl->tCK);
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for (; val <= MAX_CAS; val++)
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if ((ctrl->cas_supported >> (val - MIN_CAS)) & 1)
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break;
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if (val == (MAX_CAS + 1)) {
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ctrl->tCK++;
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continue;
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} else {
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printk(BIOS_DEBUG, "Found compatible clock, CAS pair.\n");
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break;
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}
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}
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val32 = NS2MHZ_DIV256 / ctrl->tCK;
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printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", val32);
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printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val);
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ctrl->CAS = val;
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}
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static void dram_timing(ramctr_timing *ctrl)
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{
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/* Maximum supported DDR3 frequency is 1066MHz (DDR3 2133) so make sure
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* we cap it if we have faster DIMMs.
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* Then, align it to the closest JEDEC standard frequency */
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if (ctrl->tCK <= TCK_1066MHZ) {
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ctrl->tCK = TCK_1066MHZ;
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if (ctrl->tCK == TCK_1066MHZ) {
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ctrl->edge_offset[0] = 16;
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ctrl->edge_offset[1] = 7;
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ctrl->edge_offset[2] = 7;
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@ -153,8 +202,7 @@ static void dram_timing(ramctr_timing * ctrl)
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ctrl->timC_offset[1] = 7;
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ctrl->timC_offset[2] = 7;
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ctrl->reg_320c_range_threshold = 13;
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} else if (ctrl->tCK <= TCK_933MHZ) {
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ctrl->tCK = TCK_933MHZ;
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} else if (ctrl->tCK == TCK_933MHZ) {
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ctrl->edge_offset[0] = 14;
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ctrl->edge_offset[1] = 6;
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ctrl->edge_offset[2] = 6;
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@ -162,8 +210,7 @@ static void dram_timing(ramctr_timing * ctrl)
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ctrl->timC_offset[1] = 6;
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ctrl->timC_offset[2] = 6;
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ctrl->reg_320c_range_threshold = 15;
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} else if (ctrl->tCK <= TCK_800MHZ) {
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ctrl->tCK = TCK_800MHZ;
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} else if (ctrl->tCK == TCK_800MHZ) {
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ctrl->edge_offset[0] = 13;
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ctrl->edge_offset[1] = 5;
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ctrl->edge_offset[2] = 5;
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@ -171,8 +218,7 @@ static void dram_timing(ramctr_timing * ctrl)
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ctrl->timC_offset[1] = 5;
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ctrl->timC_offset[2] = 5;
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ctrl->reg_320c_range_threshold = 15;
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} else if (ctrl->tCK <= TCK_666MHZ) {
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ctrl->tCK = TCK_666MHZ;
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} else if (ctrl->tCK == TCK_666MHZ) {
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ctrl->edge_offset[0] = 10;
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ctrl->edge_offset[1] = 4;
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ctrl->edge_offset[2] = 4;
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@ -180,8 +226,7 @@ static void dram_timing(ramctr_timing * ctrl)
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ctrl->timC_offset[1] = 4;
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ctrl->timC_offset[2] = 4;
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ctrl->reg_320c_range_threshold = 16;
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} else if (ctrl->tCK <= TCK_533MHZ) {
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ctrl->tCK = TCK_533MHZ;
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} else if (ctrl->tCK == TCK_533MHZ) {
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ctrl->edge_offset[0] = 8;
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ctrl->edge_offset[1] = 3;
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ctrl->edge_offset[2] = 3;
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@ -206,30 +251,6 @@ static void dram_timing(ramctr_timing * ctrl)
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/* DLL_CONFIG_MDLL_W_TIMER */
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ctrl->reg_5064b0 = (128000 / ctrl->tCK) + 3;
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val32 = (1000 << 8) / ctrl->tCK;
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printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", val32);
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/* Find CAS latency */
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val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK);
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printk(BIOS_DEBUG, "Minimum CAS latency : %uT\n", val);
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/* Find lowest supported CAS latency that satisfies the minimum value */
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while (!((ctrl->cas_supported >> (val - MIN_CAS)) & 1)
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&& (ctrl->cas_supported >> (val - MIN_CAS))) {
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val++;
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}
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/* Is CAS supported */
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if (!(ctrl->cas_supported & (1 << (val - MIN_CAS)))) {
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printk(BIOS_ERR, "CAS %uT not supported. ", val);
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val = MAX_CAS;
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/* Find highest supported CAS latency */
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while (!((ctrl->cas_supported >> (val - MIN_CAS)) & 1))
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val--;
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printk(BIOS_ERR, "Using CAS %uT instead.\n", val);
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}
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printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val);
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ctrl->CAS = val;
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ctrl->CWL = get_CWL(ctrl->tCK);
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printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL);
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@ -280,32 +301,18 @@ static void dram_timing(ramctr_timing * ctrl)
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static void dram_freq(ramctr_timing * ctrl)
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{
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if (ctrl->tCK > TCK_400MHZ) {
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printk (BIOS_ERR, "DRAM frequency is under lowest supported "
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"frequency (400 MHz). Increasing to 400 MHz as last resort");
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printk(BIOS_ERR, "DRAM frequency is under lowest supported "
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"frequency (400 MHz). Increasing to 400 MHz as last resort");
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ctrl->tCK = TCK_400MHZ;
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}
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while (1) {
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u8 val2;
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u32 reg1 = 0;
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/* Step 1 - Set target PCU frequency */
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if (ctrl->tCK <= TCK_1066MHZ) {
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ctrl->tCK = TCK_1066MHZ;
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} else if (ctrl->tCK <= TCK_933MHZ) {
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ctrl->tCK = TCK_933MHZ;
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} else if (ctrl->tCK <= TCK_800MHZ) {
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ctrl->tCK = TCK_800MHZ;
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} else if (ctrl->tCK <= TCK_666MHZ) {
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ctrl->tCK = TCK_666MHZ;
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} else if (ctrl->tCK <= TCK_533MHZ) {
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ctrl->tCK = TCK_533MHZ;
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} else if (ctrl->tCK <= TCK_400MHZ) {
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ctrl->tCK = TCK_400MHZ;
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} else {
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die ("No lock frequency found");
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}
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find_cas_tck(ctrl);
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/* Frequency multiplier. */
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u32 FRQ = get_FRQ(ctrl->tCK);
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@ -318,7 +325,7 @@ static void dram_freq(ramctr_timing * ctrl)
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if (val2)
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return;
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/* Step 2 - Select frequency in the MCU */
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/* Step 1 - Select frequency in the MCU */
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reg1 = FRQ;
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reg1 |= 0x80000000; // set running bit
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MCHBAR32(MC_BIOS_REQ) = reg1;
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@ -331,7 +338,7 @@ static void dram_freq(ramctr_timing * ctrl)
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}
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printk(BIOS_DEBUG, "done in %d us\n", i * 10);
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/* Step 3 - Verify lock frequency */
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/* Step 2 - Verify lock frequency */
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reg1 = MCHBAR32(MC_BIOS_DATA);
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val2 = (u8) reg1;
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if (val2 >= FRQ) {
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