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mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation 

This change uses drivers/intel/wifi chip for CNVi device and
adds dynamic SSDT entires for CNVi also export wake gpio for CNVi

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board and check for SSDT entries
for CNVi

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39315
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Srinidhi N Kaushik 2020-03-05 00:41:14 -08:00 committed by Patrick Georgi
parent 2b4ded0be8
commit dcd3d072d4
2 changed files with 10 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@ -136,7 +136,11 @@ chip soc/intel/tigerlake
device pci 14.0 on end # USB3.1 xHCI 0xA0ED
device pci 14.1 on end # USB3.1 xDCI 0xA0EE
device pci 14.2 on end # Shared RAM 0xA0EF
device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3
chip drivers/intel/wifi
register "wake" = "GPE0_PME_B0"
device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3
end
device pci 15.0 on # I2C0 0xA0E8
chip drivers/i2c/max98373
register "vmon_slot_no" = "4"

6
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@ -131,7 +131,11 @@ chip soc/intel/tigerlake
device pci 14.0 on end # USB3.1 xHCI 0xA0ED
device pci 14.1 on end # USB3.1 xDCI 0xA0EE
device pci 14.2 on end # Shared RAM 0xA0EF
device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3
chip drivers/intel/wifi
register "wake" = "GPE0_PME_B0"
device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3
end
device pci 15.0 on # I2C0 0xA0E8
chip drivers/i2c/max98373
register "vmon_slot_no" = "4"