mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation
This change uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi also export wake gpio for CNVi BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check for SSDT entries for CNVi Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39315 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -136,7 +136,11 @@ chip soc/intel/tigerlake
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device pci 14.0 on end # USB3.1 xHCI 0xA0ED
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device pci 14.0 on end # USB3.1 xHCI 0xA0ED
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device pci 14.1 on end # USB3.1 xDCI 0xA0EE
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device pci 14.1 on end # USB3.1 xDCI 0xA0EE
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device pci 14.2 on end # Shared RAM 0xA0EF
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device pci 14.2 on end # Shared RAM 0xA0EF
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device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3
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chip drivers/intel/wifi
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register "wake" = "GPE0_PME_B0"
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device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3
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end
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device pci 15.0 on # I2C0 0xA0E8
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device pci 15.0 on # I2C0 0xA0E8
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chip drivers/i2c/max98373
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chip drivers/i2c/max98373
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register "vmon_slot_no" = "4"
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register "vmon_slot_no" = "4"
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@ -131,7 +131,11 @@ chip soc/intel/tigerlake
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device pci 14.0 on end # USB3.1 xHCI 0xA0ED
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device pci 14.0 on end # USB3.1 xHCI 0xA0ED
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device pci 14.1 on end # USB3.1 xDCI 0xA0EE
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device pci 14.1 on end # USB3.1 xDCI 0xA0EE
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device pci 14.2 on end # Shared RAM 0xA0EF
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device pci 14.2 on end # Shared RAM 0xA0EF
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device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3
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chip drivers/intel/wifi
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register "wake" = "GPE0_PME_B0"
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device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3
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end
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device pci 15.0 on # I2C0 0xA0E8
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device pci 15.0 on # I2C0 0xA0E8
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chip drivers/i2c/max98373
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chip drivers/i2c/max98373
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register "vmon_slot_no" = "4"
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register "vmon_slot_no" = "4"
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