southbridge/amd sb600, sb700 & sb900 spelling fixes

Trivial fixes, but the editor highlights them, and it's easy to go
through a bunch of files while I'm otherwise idle.

Change-Id: I31333742d9c90cf6d7ae3d2f324880ed53807d7f
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7840
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

src/southbridge/amd/sb600/early_setup.c

@@ -277,7 +277,7 @@ static void sb600_devices_por_init(void)
 
 	/* sbPorAtStartOfTblCfg */
 	/* Set A-Link bridge access address. This address is set at device 14h, function 0, register 0xf0.
-	 * This is an I/O address. The I/O address must be on 16-byte boundry.  */
+	 * This is an I/O address. The I/O address must be on 16-byte boundary.  */
 	pci_write_config32(dev, 0xf0, AB_INDX);
 
 	/* To enable AB/BIF DMA access, a specific register inside the BIF register space needs to be configured first. */
@@ -301,7 +301,7 @@ static void sb600_devices_por_init(void)
 	/* set smbus 1, ASF 2.0 (Alert Standard Format), iobase */
 	pci_write_config16(dev, 0x58, SMBUS_IO_BASE | 0x11);
 
-	/* TODO: I don't know the useage of followed two lines. I copied them from CIM. */
+	/* TODO: I don't know the usage of followed two lines. I copied them from CIM. */
 	pci_write_config8(dev, 0x0a, 0x1);
 	pci_write_config8(dev, 0x0b, 0x6);
 
@@ -379,7 +379,7 @@ static void sb600_devices_por_init(void)
 	/* Arbiter enable. */
 	pci_write_config8(dev, 0x43, 0xff);
 
-	/* Set PCDMA request into hight priority list. */
+	/* Set PCDMA request into height priority list. */
 	/* pci_write_config8(dev, 0x49, 0x1) */ ;
 
 	pci_write_config8(dev, 0x40, 0x26);
@@ -483,7 +483,7 @@ static void sb600_pmio_por_init(void)
 	byte |= 1 << 1;
 	pmio_write(0x55, byte);
 
-	/* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */
+	/* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridge */
 	byte = pmio_read(0x52);
 	byte |= 1 << 6;
 	pmio_write(0x52, byte);
@@ -525,7 +525,7 @@ static void sb600_pci_cfg(void)
 
 	/* SMBus Device, BDF:0-20-0 */
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
-	/* Eable the hidden revision ID, available after A13. */
+	/* Enable the hidden revision ID, available after A13. */
 	byte = pci_read_config8(dev, 0x70);
 	byte |= (1 << 8);
 	pci_write_config8(dev, 0x70, byte);

src/southbridge/amd/sb600/lpc.c

@@ -99,7 +99,7 @@ static void sb600_lpc_read_resources(device_t dev)
 /**
  * @brief Enable resources for children devices
  *
- * @param dev the device whos children's resources are to be enabled
+ * @param dev the device whose children's resources are to be enabled
  *
  */
 static void sb600_lpc_enable_childrens_resources(device_t dev)

src/southbridge/amd/sb600/smbus.c

@@ -185,7 +185,7 @@ static void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
 	tmp |= val;
 
 	/* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */
-	outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);	/* probably we dont have to do it again. */
+	outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);	/* probably we don't have to do it again. */
 	outl(tmp, AB_DATA);
 }
 

src/southbridge/amd/sb700/early_setup.c

@@ -252,7 +252,7 @@ void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
 	byte |= 0x20;
 	pmio_write(0x8f, byte);
 
-	pmio_write(0x8b, 0x01);	/* TODO: if the HT Link is 200 MHz, it is 0x0A. It doesnt often happen. */
+	pmio_write(0x8b, 0x01);	/* TODO: if the HT Link is 200 MHz, it is 0x0A. It doesn't often happen. */
 	pmio_write(0x8a, 0x90);
 
 	pmio_write(0x88, 0x10);
@@ -374,7 +374,7 @@ static void sb700_devices_por_init(void)
 
 	/* sbPorAtStartOfTblCfg */
 	/* Set A-Link bridge access address. This address is set at device 14h, function 0, register 0xf0.
-	 * This is an I/O address. The I/O address must be on 16-byte boundry.  */
+	 * This is an I/O address. The I/O address must be on 16-byte boundary.  */
 	pci_write_config32(dev, 0xf0, AB_INDX);
 
 	/* To enable AB/BIF DMA access, a specific register inside the BIF register space needs to be configured first. */
@@ -476,7 +476,7 @@ static void sb700_devices_por_init(void)
 	pci_write_config8(dev, 0x49, 0xFF);
 	/* Enable 0x480-0x4bf, 0x4700-0x470B */
 	byte = pci_read_config8(dev, 0x4A);
-	byte |= ((1 << 1) + (1 << 6));	/*0x42, save the configuraion for port 0x80. */
+	byte |= ((1 << 1) + (1 << 6));	/*0x42, save the configuration for port 0x80. */
 	pci_write_config8(dev, 0x4A, byte);
 
 	/* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */
@@ -490,7 +490,7 @@ static void sb700_devices_por_init(void)
 	/* Arbiter enable. */
 	pci_write_config8(dev, 0x43, 0xff);
 
-	/* Set PCDMA request into hight priority list. */
+	/* Set PCDMA request into height priority list. */
 	/* pci_write_config8(dev, 0x49, 0x1) */ ;
 
 	pci_write_config8(dev, 0x40, 0x26);

src/southbridge/amd/sb700/fadt.c

@@ -62,7 +62,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
 	fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
 	fadt->gpe0_blk = ACPI_GPE0_BLK;
-	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
+	fadt->gpe1_blk = 0x0000;	/* we don't have gpe1 block, do we? */
 
 	fadt->pm1_evt_len = 4;
 	fadt->pm1_cnt_len = 2;
@@ -81,7 +81,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->duty_width = 3;
 	fadt->day_alrm = 0;	/* 0x7d these have to be */
 	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
-	fadt->century = 0;	/* 0x7f to make rtc alrm work */
+	fadt->century = 0;	/* 0x7f to make rtc alarm work */
 	fadt->iapc_boot_arch = 0x3;	/* See table 5-11 */
 	fadt->flags = 0x0001c1a5;/* 0x25; */
 

src/southbridge/amd/sb700/hda.c

@@ -53,7 +53,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
 		dword &= mask;
 	} while ((dword != val) && --count);
 
-	/* Timeout occured */
+	/* Timeout occurred */
 	if (!count)
 		return -1;
 	return 0;

src/southbridge/amd/sb700/lpc.c

@@ -140,7 +140,7 @@ static void sb700_lpc_set_resources(struct device *dev)
 
 	pci_dev_set_resources(dev);
 
-	/* Specical case. SPI Base Address. The SpiRomEnable should be set. */
+	/* Special case. SPI Base Address. The SpiRomEnable should be set. */
 	res = find_resource(dev, 0xA0);
 	pci_write_config32(dev, 0xA0, res->base | 1 << 1);
 }

src/southbridge/amd/sb700/sata.c

@@ -38,7 +38,7 @@ static int sata_drive_detect(int portnum, u16 iobar)
 		if (byte != (0xA0 + 0x10 * (portnum % 2))) {
 			/* This will happen at the first iteration of this loop
 			 * if the first SATA port is unpopulated and the
-			 * second SATA port is poulated.
+			 * second SATA port is populated.
 			 */
 			printk(BIOS_DEBUG, "drive no longer selected after %i ms, "
 				"retrying init\n", i * 10);

src/southbridge/amd/sb700/sm.c

@@ -181,7 +181,7 @@ static void sm_init(device_t dev)
 	if ((REV_SB700_A11 == rev) || REV_SB700_A12 == rev) {
 		byte |= 1 << 0;
 	}
-	/*Set bit2 to 1, enable Io port 60h read/wrire SMi trapping and
+	/*Set bit2 to 1, enable Io port 60h read/write SMi trapping and
 	 *Io port 64h write Smi trapping. conflict with ps2 keyboard
 	 */
 	//byte |= 1 << 2 | 1 << 3 | 1 << 4;

src/southbridge/amd/sb700/smbus.c

@@ -38,7 +38,7 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
 	tmp |= val;
 
 	/* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */
-	outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);	/* probably we dont have to do it again. */
+	outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);	/* probably we don't have to do it again. */
 	outl(tmp, AB_DATA);
 	reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL;
 }

src/southbridge/amd/sb800/early_setup.c

@@ -382,7 +382,7 @@ static void sb800_devices_por_init(void)
 
 	/* sbPorAtStartOfTblCfg */
 	/* rpr 4.1.Set A-Link bridge access address.
-	 * This is an I/O address. The I/O address must be on 16-byte boundry.  */
+	 * This is an I/O address. The I/O address must be on 16-byte boundary.  */
 	//pci_write_config32(dev, 0xf0, AB_INDX);
 	pmio_write(0xE0, AB_INDX & 0xFF);
 	pmio_write(0xE1, (AB_INDX >> 8) & 0xFF);
@@ -471,7 +471,7 @@ static void sb800_devices_por_init(void)
 	/* Arbiter enable. */
 	pci_write_config8(dev, 0x43, 0xff);
 
-	/* Set PCDMA request into hight priority list. */
+	/* Set PCDMA request into height priority list. */
 	/* pci_write_config8(dev, 0x49, 0x1) */ ;
 
 	pci_write_config8(dev, 0x40, 0x26);
@@ -572,7 +572,7 @@ static void sb800_pci_cfg(void)
 
 	/* LPC Device, BDF:0-20-3 */
 	/* The code below is ported from old chipset. It is not
-	 * metioned in RPR. But I keep them. The registers and the
+	 * Mentioned in RPR. But I keep them. The registers and the
 	 * comments are compatible. */
 	dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
 	/* Enabling LPC DMA function. */

src/southbridge/amd/sb800/fadt.c

@@ -62,7 +62,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
 	fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
 	fadt->gpe0_blk = ACPI_GPE0_BLK;
-	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
+	fadt->gpe1_blk = 0x0000;	/* we don't have gpe1 block, do we? */
 
 	fadt->pm1_evt_len = 4;
 	fadt->pm1_cnt_len = 2;
@@ -81,7 +81,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->duty_width = 3;
 	fadt->day_alrm = 0;	/* 0x7d these have to be */
 	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
-	fadt->century = 0;	/* 0x7f to make rtc alrm work */
+	fadt->century = 0;	/* 0x7f to make rtc alarm work */
 	fadt->iapc_boot_arch = 0x3;	/* See table 5-11 */
 	fadt->flags = 0x0001c1a5;/* 0x25; */
 

src/southbridge/amd/sb800/hda.c

@@ -53,7 +53,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
 		dword &= mask;
 	} while ((dword != val) && --count);
 
-	/* Timeout occured */
+	/* Timeout occurred */
 	if (!count)
 		return -1;
 	return 0;

src/southbridge/amd/sb800/lpc.c

@@ -113,7 +113,7 @@ static void sb800_lpc_set_resources(struct device *dev)
 
 	pci_dev_set_resources(dev);
 
-	/* Specical case. SPI Base Address. The SpiRomEnable should be set. */
+	/* Special case. SPI Base Address. The SpiRomEnable should be set. */
 	res = find_resource(dev, 0xA0);
 	pci_write_config32(dev, 0xA0, res->base | 1 << 1);
 
@@ -122,7 +122,7 @@ static void sb800_lpc_set_resources(struct device *dev)
 /**
  * @brief Enable resources for children devices
  *
- * @param dev the device whos children's resources are to be enabled
+ * @param dev the device whose children's resources are to be enabled
  *
  */
 static void sb800_lpc_enable_childrens_resources(device_t dev)

src/southbridge/amd/sb800/sata.c

@@ -38,7 +38,7 @@ static int sata_drive_detect(int portnum, u16 iobar)
 		if (byte != (0xA0 + 0x10 * (portnum % 2))) {
 			/* This will happen at the first iteration of this loop
 			 * if the first SATA port is unpopulated and the
-			 * second SATA port is poulated.
+			 * second SATA port is populated.
 			 */
 			printk(BIOS_DEBUG, "drive no longer selected after %i ms, "
 				"retrying init\n", i * 10);
@@ -97,7 +97,7 @@ static void sata_init(struct device *dev)
 	/* get rev_id */
 	rev_id = pci_read_config8(sm_dev, 0x08) - 0x2F;
 
-	/* get base addresss */
+	/* get base address */
 	sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
 	sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
 	sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;

src/southbridge/amd/sb800/sm.c

@@ -313,7 +313,7 @@ static void sb800_sm_set_resources(struct device *dev)
 	pci_dev_set_resources(dev);
 
 
-	/* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */
+	/* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridge */
 	byte = pm_ioread(0x52);
 	byte |= 1 << 6;
 	pm_iowrite(0x52, byte);

src/southbridge/amd/sb800/smbus.c

@@ -196,7 +196,7 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr,
 	tmp |= val;
 
 	/* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */
-	outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);	/* probably we dont have to do it again. */
+	outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);	/* probably we don't have to do it again. */
 	outl(tmp, AB_DATA);
 	outl(0, AB_INDX);
 }
@@ -218,7 +218,7 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port,
 	tmp |= val;
 
 	//printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr);
-	outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);	/* probably we dont have to do it again. */
+	outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);	/* probably we don't have to do it again. */
 	outl(tmp, AB_DATA);
 	outl(0, AB_INDX);
 }

src/southbridge/amd/sb800/usb.c

@@ -71,7 +71,7 @@ static void usb_init2(struct device *dev)
 	usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF;
 	printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0);
 
-	/* RPR7.3 Enables the USB PHY auto calibration resister to match 45ohm resistence */
+	/* RPR7.3 Enables the USB PHY auto calibration resister to match 45ohm resistance */
 	dword = 0x00020F00;
 	write32(usb2_bar0 + 0xC0, dword);