From dcf30e837b35bbf698231c8a27fd66cdf966fb36 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Tue, 22 Mar 2022 09:02:16 +0100
Subject: [PATCH] soc/intel/denverton_ns: Resolve macro conflicts with UDK2017
 headers

Replace LShiftU64 and RShiftU64 as the defined macro conflicts with
UDK2017 headers.

Tested using timeless builds: The produced binaries are identical.

Change-Id: I8f205f663be9c9c31cf384ca89370afa48ca1e15
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
---
 src/soc/intel/denverton_ns/gpio_dnv.c         | 34 +++++++------------
 .../intel/denverton_ns/include/soc/gpio_dnv.h |  3 --
 2 files changed, 13 insertions(+), 24 deletions(-)

diff --git a/src/soc/intel/denverton_ns/gpio_dnv.c b/src/soc/intel/denverton_ns/gpio_dnv.c
index 70138d3ed7..299f950968 100644
--- a/src/soc/intel/denverton_ns/gpio_dnv.c
+++ b/src/soc/intel/denverton_ns/gpio_dnv.c
@@ -425,24 +425,19 @@ void gpio_configure_dnv_pads(const struct dnv_pad_config *gpio, size_t num)
 		//
 		// Update value to be programmed in HOSTSW_OWN register
 		//
-		HostSoftOwnRegMask[GroupIndex] |= LShiftU64(
-			(uint64_t)GpioData->GpioConfig.HostSoftPadOwn & 0x1,
-			PadNumber);
-		HostSoftOwnReg[GroupIndex] |= LShiftU64(
-			(uint64_t)GpioData->GpioConfig.HostSoftPadOwn >> 0x1,
-			PadNumber);
+		HostSoftOwnRegMask[GroupIndex] |=
+			((uint64_t)GpioData->GpioConfig.HostSoftPadOwn & 0x1) << PadNumber;
+		HostSoftOwnReg[GroupIndex] |=
+			((uint64_t)GpioData->GpioConfig.HostSoftPadOwn >> 0x1) << PadNumber;
 
 		//
 		// Update value to be programmed in GPI_GPE_EN register
 		//
-		GpiGpeEnRegMask[GroupIndex] |= LShiftU64(
-			(uint64_t)(GpioData->GpioConfig.InterruptConfig & 0x1),
-			PadNumber);
-		GpiGpeEnReg[GroupIndex] |= LShiftU64(
-			(uint64_t)(GpioData->GpioConfig.InterruptConfig &
-				   GpioIntSci) >>
-				3,
-			PadNumber);
+		GpiGpeEnRegMask[GroupIndex] |=
+			((uint64_t)GpioData->GpioConfig.InterruptConfig & 0x1) << PadNumber;
+		GpiGpeEnReg[GroupIndex] |=
+			(((uint64_t)GpioData->GpioConfig.InterruptConfig & GpioIntSci) >> 3)
+			<< PadNumber;
 	}
 
 	for (Index = 0; Index < NumberOfGroups; Index++) {
@@ -463,10 +458,8 @@ void gpio_configure_dnv_pads(const struct dnv_pad_config *gpio, size_t num)
 					GpioGroupInfo[Index].Community,
 					GpioGroupInfo[Index].HostOwnOffset +
 						0x4),
-				~(uint32_t)(RShiftU64(HostSoftOwnRegMask[Index],
-						      32)),
-				(uint32_t)(
-					RShiftU64(HostSoftOwnReg[Index], 32)));
+				~(uint32_t)(HostSoftOwnRegMask[Index] >> 32),
+				(uint32_t)(HostSoftOwnReg[Index] >> 32));
 		}
 
 		//
@@ -486,9 +479,8 @@ void gpio_configure_dnv_pads(const struct dnv_pad_config *gpio, size_t num)
 					GpioGroupInfo[Index].Community,
 					GpioGroupInfo[Index].GpiGpeEnOffset +
 						0x4),
-				~(uint32_t)(
-					RShiftU64(GpiGpeEnRegMask[Index], 32)),
-				(uint32_t)(RShiftU64(GpiGpeEnReg[Index], 32)));
+				~(uint32_t)(GpiGpeEnRegMask[Index] >> 32),
+				(uint32_t)(GpiGpeEnReg[Index] >> 32));
 		}
 	}
 }
diff --git a/src/soc/intel/denverton_ns/include/soc/gpio_dnv.h b/src/soc/intel/denverton_ns/include/soc/gpio_dnv.h
index 447064d913..06a0721fa1 100644
--- a/src/soc/intel/denverton_ns/include/soc/gpio_dnv.h
+++ b/src/soc/intel/denverton_ns/include/soc/gpio_dnv.h
@@ -3,9 +3,6 @@
 #ifndef _DENVERTON_NS_GPIO_H_
 #define _DENVERTON_NS_GPIO_H_
 
-#define RShiftU64(Operand, Count) (Operand >> Count)
-#define LShiftU64(Operand, Count) (Operand << Count)
-
 #include <soc/gpio_defs.h>
 
 #ifndef __ACPI__