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soc/intel/cannonlake: Sort Kconfig for Cannonlake 

Look and feel update, sort the sequence in Kconfig.

Change-Id: I41d99979d9c7d081086aac8bfef27186b37a6e70
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lijian Zhao 2017-07-30 15:40:10 -07:00 committed by Martin Roth
parent ea5336d240
commit dcf99b0445
1 changed files with 15 additions and 15 deletions
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30
src/soc/intel/cannonlake/Kconfig
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@ -8,37 +8,37 @@ if SOC_INTEL_CANNONLAKE
config CPU_SPECIFIC_OPTIONS config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select ARCH_BOOTBLOCK_X86_32 select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32
select SOC_INTEL_COMMON_BLOCK_TIMER select ARCH_VERSTAGE_X86_32
select HAVE_MONOTONIC_TIMER
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select UDELAY_TSC
select REG_SCRIPT
select C_ENVIRONMENT_BOOTBLOCK select C_ENVIRONMENT_BOOTBLOCK
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select HAVE_HARD_RESET select HAVE_HARD_RESET
select HAVE_INTEL_FIRMWARE select HAVE_INTEL_FIRMWARE
select HAVE_MONOTONIC_TIMER
select INTEL_CAR_NEM_ENHANCED select INTEL_CAR_NEM_ENHANCED
select PLATFORM_USES_FSP2_0 select PLATFORM_USES_FSP2_0
select REG_SCRIPT
select RELOCATABLE_RAMSTAGE select RELOCATABLE_RAMSTAGE
select SOC_INTEL_COMMON select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CAR
select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_LPSS
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_SMBUS
select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_CSE
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GPIO
select SOC_INTEL_COMMON_BLOCK_LPSS
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SMBUS
select SOC_INTEL_COMMON_BLOCK_TIMER
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_RESET
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select UDELAY_TSC
config UART_DEBUG config UART_DEBUG
bool "Enable UART debug port." bool "Enable UART debug port."