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soc/amd/common/include/espi: reduce visibility of IO/MMIO decode defines

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The eSPI decode range defines aren't and shouldn't be used directly from
outside of the common AMD eSPI code which provides functions to abstract
the register access, so move the defines from amdblocks/espi.h to
espi_def.h inside the common AMD LPC/eSPI support directory to limit the
visibility. The special I/O range decode bits need to stay in
amdblocks/espi.h since those are used in the devicetree. Also update the
indentation in espi_def.h so that the defines line up properly.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic4ea30a1a6f10e94d88bf3b29f86dee2da6b39b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64053
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2022-05-04 17:43:46 +02:00
parent 2e4b95da88
commit dd14a623b1
2 changed files with 63 additions and 60 deletions
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18
src/soc/amd/common/block/include/amdblocks/espi.h
View file

@ -9,27 +9,11 @@
#define ESPI_OFFSET_FROM_BAR 0x10000 #define ESPI_OFFSET_FROM_BAR 0x10000
#define ESPI_DECODE 0x40 #define ESPI_DECODE 0x40
#define ESPI_DECODE_MMIO_RANGE_EN(range) (1 << (((range) & 3) + 12)) /* more bits defined in soc/common/amd/blocks/lpc/espi_def.h */
#define ESPI_DECODE_IO_RANGE_EN(range) (1 << (((range) & 3) + 8))
#define ESPI_DECODE_IO_0x80_EN (1 << 2) #define ESPI_DECODE_IO_0x80_EN (1 << 2)
#define ESPI_DECODE_IO_0X60_0X64_EN (1 << 1) #define ESPI_DECODE_IO_0X60_0X64_EN (1 << 1)
#define ESPI_DECODE_IO_0X2E_0X2F_EN (1 << 0) #define ESPI_DECODE_IO_0X2E_0X2F_EN (1 << 0)
#define ESPI_IO_BASE_REG0 0x44
#define ESPI_IO_BASE_REG1 0x48
#define ESPI_IO_SIZE0 0x4c
#define ESPI_MMIO_BASE_REG0 0x50
#define ESPI_MMIO_BASE_REG1 0x54
#define ESPI_MMIO_BASE_REG2 0x58
#define ESPI_MMIO_BASE_REG3 0x5c
#define ESPI_MMIO_SIZE_REG0 0x60
#define ESPI_MMIO_SIZE_REG1 0x64
#define ESPI_IO_RANGE_BASE_REG(base, range) ((base) + ((range) & 3) * 2)
#define ESPI_IO_RANGE_SIZE_REG(base, range) ((base) + ((range) & 3))
#define ESPI_MMIO_RANGE_BASE_REG(base, range) ((base) + ((range) & 3) * 4)
#define ESPI_MMIO_RANGE_SIZE_REG(base, range) ((base) + ((range) & 3) * 2)
#define ESPI_GENERIC_IO_WIN_COUNT 4 #define ESPI_GENERIC_IO_WIN_COUNT 4
#define ESPI_GENERIC_IO_MAX_WIN_SIZE 0x100 #define ESPI_GENERIC_IO_MAX_WIN_SIZE 0x100
#define ESPI_GENERIC_MMIO_WIN_COUNT 4 #define ESPI_GENERIC_MMIO_WIN_COUNT 4

19
src/soc/amd/common/block/lpc/espi_def.h
View file

@ -40,6 +40,20 @@
#define ESPI_BUS_MASTER_EN (1 << 1) #define ESPI_BUS_MASTER_EN (1 << 1)
#define ESPI_SW_RST (1 << 0) #define ESPI_SW_RST (1 << 0)
/* bits in ESPI_DECODE 0x40 */
#define ESPI_DECODE_MMIO_RANGE_EN(range) (1 << (((range) & 3) + 12))
#define ESPI_DECODE_IO_RANGE_EN(range) (1 << (((range) & 3) + 8))
#define ESPI_IO_BASE_REG0 0x44
#define ESPI_IO_BASE_REG1 0x48
#define ESPI_IO_SIZE0 0x4c
#define ESPI_MMIO_BASE_REG0 0x50
#define ESPI_MMIO_BASE_REG1 0x54
#define ESPI_MMIO_BASE_REG2 0x58
#define ESPI_MMIO_BASE_REG3 0x5c
#define ESPI_MMIO_SIZE_REG0 0x60
#define ESPI_MMIO_SIZE_REG1 0x64
#define ESPI_SLAVE0_INT_EN 0x6c #define ESPI_SLAVE0_INT_EN 0x6c
#define ESPI_SLAVE0_INT_STS 0x70 #define ESPI_SLAVE0_INT_STS 0x70
#define ESPI_STATUS_DNCMD_COMPLETE (1 << 28) #define ESPI_STATUS_DNCMD_COMPLETE (1 << 28)
@ -52,4 +66,9 @@
#define ESPI_RXVW_POLARITY 0xac #define ESPI_RXVW_POLARITY 0xac
#define ESPI_IO_RANGE_BASE_REG(base, range) ((base) + ((range) & 3) * 2)
#define ESPI_IO_RANGE_SIZE_REG(base, range) ((base) + ((range) & 3))
#define ESPI_MMIO_RANGE_BASE_REG(base, range) ((base) + ((range) & 3) * 4)
#define ESPI_MMIO_RANGE_SIZE_REG(base, range) ((base) + ((range) & 3) * 2)
#endif /* AMD_BLOCK_ESPI_DEF_H */ #endif /* AMD_BLOCK_ESPI_DEF_H */