mb/lenovo: Add additional FMAPs on 8MiB devices

* Add FMAP for measured boot only, with a single RO partition.
* Add FMAP for measured boot only, with a single RO partition
  but where the ME has been shrunken.

Tested on X220 using VBOOT+measured boot:
* Used patched IFD and ME, boots into OS

Change-Id: I04c1add13198444638c669deec1e05159b1a09c9
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
This commit is contained in:
Marcello Sylvester Bauer 2020-02-19 10:05:33 +01:00 committed by Patrick Georgi
parent 15161d9284
commit dd1a0acc4a
8 changed files with 176 additions and 0 deletions

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@ -0,0 +1,22 @@
FLASH@0xff800000 0x800000 {
SI_ALL 0x20000 {
SI_DESC 0x1000
SI_GBE 0x2000
SI_ME
}
SI_BIOS 0x7e0000 {
UNIFIED_MRC_CACHE 0x20000 {
RECOVERY_MRC_CACHE 0x10000
RW_MRC_CACHE 0x10000
}
WP_RO {
FMAP 0x800
RO_FRID 0x40
RO_PADDING 0x7c0
RO_VPD(PRESERVE) 0x1000
GBB 0x1e000
COREBOOT(CBFS)
}
}
}

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@ -0,0 +1,22 @@
FLASH@0xff800000 0x800000 {
SI_ALL 0x500000 {
SI_DESC 0x1000
SI_GBE 0x2000
SI_ME 0x4ed000
}
SI_BIOS 0x300000 {
UNIFIED_MRC_CACHE 0x20000 {
RECOVERY_MRC_CACHE 0x10000
RW_MRC_CACHE 0x10000
}
WP_RO {
FMAP 0x800
RO_FRID 0x40
RO_PADDING 0x7c0
RO_VPD(PRESERVE) 0x1000
GBB 0x1e000
COREBOOT(CBFS)
}
}
}

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@ -0,0 +1,22 @@
FLASH@0xff800000 0x800000 {
SI_ALL 0x20000 {
SI_DESC 0x1000
SI_GBE 0x2000
SI_ME
}
SI_BIOS 0x7e0000 {
UNIFIED_MRC_CACHE 0x20000 {
RECOVERY_MRC_CACHE 0x10000
RW_MRC_CACHE 0x10000
}
WP_RO {
FMAP 0x800
RO_FRID 0x40
RO_PADDING 0x7c0
RO_VPD(PRESERVE) 0x1000
GBB 0x1e000
COREBOOT(CBFS)
}
}
}

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@ -0,0 +1,22 @@
FLASH@0xff800000 0x800000 {
SI_ALL 0x500000 {
SI_DESC 0x1000
SI_GBE 0x2000
SI_ME 0x4ed000
}
SI_BIOS 0x300000 {
UNIFIED_MRC_CACHE 0x20000 {
RECOVERY_MRC_CACHE 0x10000
RW_MRC_CACHE 0x10000
}
WP_RO {
FMAP 0x800
RO_FRID 0x40
RO_PADDING 0x7c0
RO_VPD(PRESERVE) 0x1000
GBB 0x1e000
COREBOOT(CBFS)
}
}
}

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@ -0,0 +1,22 @@
FLASH@0xff800000 0x800000 {
SI_ALL 0x20000 {
SI_DESC 0x1000
SI_GBE 0x2000
SI_ME
}
SI_BIOS 0x7e0000 {
UNIFIED_MRC_CACHE 0x20000 {
RECOVERY_MRC_CACHE 0x10000
RW_MRC_CACHE 0x10000
}
WP_RO {
FMAP 0x800
RO_FRID 0x40
RO_PADDING 0x7c0
RO_VPD(PRESERVE) 0x1000
GBB 0x1e000
COREBOOT(CBFS)
}
}
}

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@ -0,0 +1,22 @@
FLASH@0xff800000 0x800000 {
SI_ALL 0x500000 {
SI_DESC 0x1000
SI_GBE 0x2000
SI_ME 0x4ed000
}
SI_BIOS 0x300000 {
UNIFIED_MRC_CACHE 0x20000 {
RECOVERY_MRC_CACHE 0x10000
RW_MRC_CACHE 0x10000
}
WP_RO {
FMAP 0x800
RO_FRID 0x40
RO_PADDING 0x7c0
RO_VPD(PRESERVE) 0x1000
GBB 0x1e000
COREBOOT(CBFS)
}
}
}

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@ -0,0 +1,22 @@
FLASH@0xff800000 0x800000 {
SI_ALL 0x20000 {
SI_DESC 0x1000
SI_GBE 0x2000
SI_ME
}
SI_BIOS 0x7e0000 {
UNIFIED_MRC_CACHE 0x20000 {
RECOVERY_MRC_CACHE 0x10000
RW_MRC_CACHE 0x10000
}
WP_RO {
FMAP 0x800
RO_FRID 0x40
RO_PADDING 0x7c0
RO_VPD(PRESERVE) 0x1000
GBB 0x1e000
COREBOOT(CBFS)
}
}
}

View File

@ -0,0 +1,22 @@
FLASH@0xff800000 0x800000 {
SI_ALL 0x500000 {
SI_DESC 0x1000
SI_GBE 0x2000
SI_ME 0x4ed000
}
SI_BIOS 0x300000 {
UNIFIED_MRC_CACHE 0x20000 {
RECOVERY_MRC_CACHE 0x10000
RW_MRC_CACHE 0x10000
}
WP_RO {
FMAP 0x800
RO_FRID 0x40
RO_PADDING 0x7c0
RO_VPD(PRESERVE) 0x1000
GBB 0x1e000
COREBOOT(CBFS)
}
}
}