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soc/intel/gma: Move DDI-A 4-lane config to common code 

Change-Id: I0572dbbfb61e5e0129fe6a3a1b5894145d74fd0d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40728
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber 2020-04-26 20:37:32 +02:00
parent dd59762729
commit dd274e2971
6 changed files with 18 additions and 37 deletions
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3
src/soc/intel/cannonlake/Kconfig
View File

@ -25,6 +25,7 @@ config SOC_INTEL_COFFEELAKE
select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK
select HAVE_INTEL_FSP_REPO
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
help
Intel Coffeelake support
@ -33,6 +34,7 @@ config SOC_INTEL_WHISKEYLAKE
select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK
select HAVE_INTEL_FSP_REPO
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
help
Intel Whiskeylake support
@ -41,6 +43,7 @@ config SOC_INTEL_COMETLAKE
select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK
select HAVE_INTEL_FSP_REPO
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
help
Intel Cometlake support

17
src/soc/intel/cannonlake/graphics.c
View File

@ -11,20 +11,3 @@ uintptr_t fsp_soc_get_igd_bar(void)
{
return graphics_get_memory_base();
}
void graphics_soc_init(struct device *dev)
{
uint32_t ddi_buf_ctl;
/*
* Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
* This will allow the kernel to use 4-lane eDP links properly
* if the VBIOS or GOP driver do not execute.
*/
ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);
if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) {
ddi_buf_ctl |= (DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED |
DDI_BUF_IS_IDLE);
graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
}
}

5
src/soc/intel/common/block/graphics/Kconfig
View File

@ -2,3 +2,8 @@ config SOC_INTEL_COMMON_BLOCK_GRAPHICS
bool
help
Intel Processor common Graphics support
config SOC_INTEL_CONFIGURE_DDI_A_4_LANES
bool
help
Selected by platforms that require DDI-A bifurcation setup.

8
src/soc/intel/common/block/graphics/graphics.c
View File

@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi.h>
#include <assert.h>
#include <bootmode.h>
#include <console/console.h>
@ -34,6 +35,13 @@ static void gma_init(struct device *const dev)
/* SoC specific configuration. */
graphics_soc_init(dev);
if (CONFIG(SOC_INTEL_CONFIGURE_DDI_A_4_LANES) && !acpi_is_wakeup_s3()) {
const u32 ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);
/* Only program if the buffer is not enabled yet. */
if (!(ddi_buf_ctl & DDI_BUF_CTL_ENABLE))
graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl | DDI_A_4_LANES);
}
/*
* GFX PEIM module inside FSP binary is taking care of graphics
* initialization based on RUN_FSP_GOP Kconfig option and input

1
src/soc/intel/skylake/Kconfig
View File

@ -74,6 +74,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_MONOTONIC_TIMER

21
src/soc/intel/skylake/graphics.c
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <device/mmio.h>
@ -16,7 +15,7 @@ uintptr_t fsp_soc_get_igd_bar(void)
return graphics_get_memory_base();
}
static void graphics_setup_panel(struct device *dev)
void graphics_soc_init(struct device *dev)
{
struct soc_intel_skylake_config *conf = config_of(dev);
struct resource *mmio_res;
@ -76,24 +75,6 @@ static void graphics_setup_panel(struct device *dev)
}
}
void graphics_soc_init(struct device *dev)
{
u32 ddi_buf_ctl;
graphics_setup_panel(dev);
/*
* Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
* This will allow the kernel to use 4-lane eDP links properly
* if the VBIOS or GOP driver does not execute.
*/
ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);
if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) {
ddi_buf_ctl |= DDI_A_4_LANES;
graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
}
}
const struct i915_gpu_controller_info *
intel_igd_get_controller_info(const struct device *device)
{