superio/fintek/f71869ad: Configure multi-func reg in devicetree

Facilitate for the configuration of so called "Multi-function Select
Registers" with devicetree.cb in ramstage.

Make use of this new functionality in, mainboard/jetway/nf81-t56n-lf to
correctly configure the Fintek's multiplexed GPIO pins to be in AMD TSI
mode. This allows the Fintek to correctly talk to the Southbridge over
the SMBus for CPU temperature data as to control fans and so on.

Change-Id: I80abcd8b767fc4b22d00d1384ce4ef89fe837e3d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5576
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)

src/mainboard/jetway/nf81-t56n-lf/devicetree.cb

@@ -56,6 +56,11 @@ chip northbridge/amd/agesa/family14/root_complex
 						device pci 14.2 on end # HDA	0x4383
 						device pci 14.3 on # LPC		0x439d
 							chip superio/fintek/f71869ad
+								register "multi_function_register_1" = "0x01"
+								register "multi_function_register_2" = "0x6f"
+								register "multi_function_register_3" = "0x24"
+								register "multi_function_register_4" = "0x00"
+								register "multi_function_register_5" = "0x60"
 # XXX: 4e is the default index port and .xy is the
 # LDN indexing the pnp_info array found in the superio.c
 # NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124,

src/superio/fintek/f71869ad/Makefile.inc

@@ -18,4 +18,5 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += f71869ad_multifunc.c
 ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += superio.c

src/superio/fintek/f71869ad/chip.h

@@ -22,9 +22,17 @@
 #define SUPERIO_FINTEK_F71869AD_CHIP_H
 
 #include <pc80/keyboard.h>
+#include <stdint.h>
 
 struct superio_fintek_f71869ad_config {
 	struct pc_keyboard keyboard;
+
+	/* Member variables are defined in devicetree.cb. */
+	uint8_t multi_function_register_1;
+	uint8_t multi_function_register_2;
+	uint8_t multi_function_register_3;
+	uint8_t multi_function_register_4;
+	uint8_t multi_function_register_5;
 };
 
 #endif /* SUPERIO_FINTEK_F71869AD_CHIP_H */

src/superio/fintek/f71869ad/f71869ad_multifunc.c

@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include "chip.h"
+#include "fintek_internal.h"
+
+#define MULTI_FUNC_SEL_REG1 0x28
+#define MULTI_FUNC_SEL_REG2 0x29
+#define MULTI_FUNC_SEL_REG3 0x2A
+#define MULTI_FUNC_SEL_REG4 0x2B
+#define MULTI_FUNC_SEL_REG5 0x2C
+
+void f71869ad_multifunc_init(device_t dev)
+{
+	struct superio_fintek_f71869ad_config *conf = dev->chip_info;
+
+	pnp_enter_conf_mode(dev);
+
+	/* multi-func select reg1 */
+	pnp_write_config(dev, MULTI_FUNC_SEL_REG1,
+			conf->multi_function_register_1);
+
+	/* multi-func select reg2 (CLK_TUNE_EN=0) */
+	pnp_write_config(dev, MULTI_FUNC_SEL_REG2,
+			conf->multi_function_register_2);
+
+	/* multi-func select reg3 (CLK_TUNE_EN=0) */
+	pnp_write_config(dev, MULTI_FUNC_SEL_REG3,
+			conf->multi_function_register_3);
+
+	/* multi-func select reg4 (CLK_TUNE_EN=0) */
+	pnp_write_config(dev, MULTI_FUNC_SEL_REG4,
+			conf->multi_function_register_4);
+
+	/* multi-func select reg5 (CLK_TUNE_EN=0) */
+	pnp_write_config(dev, MULTI_FUNC_SEL_REG5,
+			conf->multi_function_register_5);
+
+	pnp_exit_conf_mode(dev);
+}

src/superio/fintek/f71869ad/fintek_internal.h

@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SUPERIO_FINTEK_F71869AD_INTERNAL_H
+#define SUPERIO_FINTEK_F71869AD_INTERNAL_H
+
+#include <arch/io.h>
+#include <device/pnp.h>
+
+void f71869ad_multifunc_init(device_t dev);
+
+#endif /* SUPERIO_FINTEK_F71869AD_INTERNAL_H */

src/superio/fintek/f71869ad/superio.c

@@ -25,6 +25,7 @@
 #include <console/console.h>
 #include <stdlib.h>
 
+#include "fintek_internal.h"
 #include "chip.h"
 #include "f71869ad.h"
 
@@ -40,6 +41,9 @@ static void f71869ad_init(device_t dev)
 	case F71869AD_KBC:
 		pc_keyboard_init(&conf->keyboard);
 		break;
+	case F71869AD_HWM:
+		f71869ad_multifunc_init(dev);
+		break;
 	}
 }