From dd2f3fa533eb8f7537aa480b20d9bbf61f01d6a7 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Mon, 8 Feb 2021 22:23:54 +0100
Subject: [PATCH] soc/amd/picasso/cpu: move get_cpu_count to common code

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0690787f492d764a20a4219822eb10fb5cd86de0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
---
 src/soc/amd/common/block/cpu/noncar/Makefile.inc | 1 +
 src/soc/amd/common/block/cpu/noncar/cpu.c        | 9 +++++++++
 src/soc/amd/common/block/include/amdblocks/cpu.h | 1 +
 src/soc/amd/picasso/acpi.c                       | 2 +-
 src/soc/amd/picasso/agesa_acpi.c                 | 2 +-
 src/soc/amd/picasso/cpu.c                        | 6 +-----
 src/soc/amd/picasso/include/soc/cpu.h            | 1 -
 7 files changed, 14 insertions(+), 8 deletions(-)
 create mode 100644 src/soc/amd/common/block/cpu/noncar/cpu.c

diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc
index dd959417f1..808679dfea 100644
--- a/src/soc/amd/common/block/cpu/noncar/Makefile.inc
+++ b/src/soc/amd/common/block/cpu/noncar/Makefile.inc
@@ -3,6 +3,7 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR),y)
 bootblock-y += pre_c.S
 bootblock-y += write_resume_eip.c
 romstage-y += memmap.c
+ramstage-y += cpu.c
 ramstage-y += memmap.c
 
 endif # CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR
diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c
new file mode 100644
index 0000000000..7c1daf96f1
--- /dev/null
+++ b/src/soc/amd/common/block/cpu/noncar/cpu.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/cpu.h>
+#include <cpu/cpu.h>
+
+int get_cpu_count(void)
+{
+	return 1 + (cpuid_ecx(0x80000008) & 0xff);
+}
diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h
index 0a93643e2a..50300d5a0f 100644
--- a/src/soc/amd/common/block/include/amdblocks/cpu.h
+++ b/src/soc/amd/common/block/include/amdblocks/cpu.h
@@ -3,6 +3,7 @@
 #ifndef AMD_BLOCK_CPU_H
 #define AMD_BLOCK_CPU_H
 
+int get_cpu_count(void);
 void write_resume_eip(void);
 
 #endif /* AMD_BLOCK_CPU_H */
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index eba9dfee3d..2f08dce852 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -19,9 +19,9 @@
 #include <device/pci.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/acpi.h>
+#include <amdblocks/cpu.h>
 #include <soc/acpi.h>
 #include <soc/pci_devs.h>
-#include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/southbridge.h>
 #include <soc/nvs.h>
diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c
index 6020ec0017..119dd55b89 100644
--- a/src/soc/amd/picasso/agesa_acpi.c
+++ b/src/soc/amd/picasso/agesa_acpi.c
@@ -12,7 +12,7 @@
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
-#include <soc/cpu.h>
+#include <amdblocks/cpu.h>
 #include <soc/data_fabric.h>
 #include <soc/pci_devs.h>
 #include <stdlib.h>
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index 5979fc6a82..b18a3b4641 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/cpu.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/mtrr.h>
@@ -41,11 +42,6 @@ static void pre_mp_init(void)
 	x86_mtrr_check();
 }
 
-int get_cpu_count(void)
-{
-	return 1 + (cpuid_ecx(0x80000008) & 0xff);
-}
-
 static void set_cstate_io_addr(void)
 {
 	msr_t cst_addr;
diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h
index 3f6cd247c2..79d5cc6536 100644
--- a/src/soc/amd/picasso/include/soc/cpu.h
+++ b/src/soc/amd/picasso/include/soc/cpu.h
@@ -3,7 +3,6 @@
 #ifndef AMD_PICASSO_CPU_H
 #define AMD_PICASSO_CPU_H
 
-int get_cpu_count(void);
 void check_mca(void);
 
 #define RAVEN1_B0_CPUID			0x00810f10