qcs405: Add support for USB host mode
Add required changes for USB host mode for USB disk enumeration. TEST=build & run Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Signed-off-by: Vijayavardhan Vennapusa <vvreddy@partner-android.googlesource.com> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Vijayavardhan Vennapusa
Patrick Georgi
parent
1d94849e74
commit
dd3cffdb0c
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@ -21,6 +21,7 @@ romstage-y += spi.c
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romstage-y += cbmem.c
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romstage-y += gpio.c
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romstage-y += clock.c
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romstage-y += usb.c
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################################################################################
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ramstage-y += soc.c
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@ -29,6 +30,7 @@ ramstage-y += spi.c
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ramstage-y += cbmem.c
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ramstage-y += gpio.c
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ramstage-y += clock.c
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ramstage-y += usb.c
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################################################################################
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@ -26,10 +26,10 @@
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/**
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* USB BCR registers
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*/
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#define GCC_USB_HS_PHY_CFG_AHB_BCR 0x1841038
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#define GCC_USB_HS_PHY_CFG_AHB_BCR 0x180000C
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#define GCC_USB_HS_BCR 0x1841000
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#define GCC_USB_30_BCR 0x1839000
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#define GCC_USB2A_PHY_BCR 0x1841028
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#define GCC_USB2A_PHY_BCR 0x180000C
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#define GCC_USB2_HS_PHY_ONLY_BCR 0x1841034
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#define GCC_QUSB2_PHY_BCR 0x184103C
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@ -0,0 +1,78 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (c) 2018 Qualcomm Technologies
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <types.h>
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#ifndef _QCS405_USB_H_
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#define _QCS405_USB_H_
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/* QSCRATCH_GENERAL_CFG register bit offset */
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#define PIPE_UTMI_CLK_SEL BIT(0)
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#define PIPE3_PHYSTATUS_SW BIT(3)
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#define PIPE_UTMI_CLK_DIS BIT(8)
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/* Global USB3 Control Registers */
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#define DWC3_GUSB3PIPECTL_DELAYP1TRANS BIT(18)
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#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX BIT(27)
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#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
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#define DWC3_GCTL_PRTCAP_OTG 3
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#define DWC3_GCTL_PRTCAP_HOST 1
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/* Global USB2 PHY Configuration Register */
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#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10)
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#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
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#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3)
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#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
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#define USBTRDTIM_UTMI_8_BIT 9
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#define UTMI_PHYIF_8_BIT 0
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#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
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#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
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#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
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#define DWC3_GCTL_U2EXIT_LFPS (1 << 2)
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#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
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/* USB2 PHY register values */
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#define USB2PHY_TCSR_CTRL 0x01
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#define USB2PHY_REFCLK_CTRL 0x0d
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#define USB2PHY_UTMI_CTRL5 0x12
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#define USB2PHY_PARAMETER_OVERRIDE_X0 0x63
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#define USB2PHY_PARAMETER_OVERRIDE_X1 0x03
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#define USB2PHY_PARAMETER_OVERRIDE_X2 0x1d
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#define USB2PHY_PARAMETER_OVERRIDE_X3 0x03
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#define USB2PHY_HS_PHY_CTRL1 0x23
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#define QUSB2PHY_HS_PHY_CTRL_COMMON0 0x08
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#define QUSB2PHY_HS_PHY_CTRL_COMMON1 0xdc
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#define USB2PHY_HS_PHY_CTRL2 0xe0
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#define USB2PHY_UTMI_CTRL5_POR_CLEAR 0x10
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#define USB2PHY_HS_PHY_CTRL2_SUSPEND_N_SEL 0x60
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struct usb_board_data {
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/* Register values going to override from the boardfile */
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u8 parameter_override_x0;
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u8 parameter_override_x1;
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u8 parameter_override_x2;
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u8 parameter_override_x3;
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};
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enum usb_port {
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HSUSB_SS_PORT_0,
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HSUSB_HS_PORT_1,
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};
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void setup_usb_host(enum usb_port port, struct usb_board_data *data);
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/* Call reset_ before setup_ */
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void reset_usb(enum usb_port port);
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#endif /* _QCS405_USB_H_ */
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@ -0,0 +1,269 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (c) 2018 Qualcomm Technologies
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/mmio.h>
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#include <lib.h>
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#include <stdlib.h>
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#include <console/console.h>
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#include <delay.h>
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#include <soc/usb.h>
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#include <soc/clock.h>
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#include <timer.h>
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/* USB BASE ADDRESS */
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#define USB_HOST0_DWC3_BASE 0x758C100
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#define USB3_USB30_QSCRATCH_BASE 0x7678800
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#define USB2_FEMTO_PHY_PRI_BASE 0x007A000
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#define USB_HOST1_DWC3_BASE 0x78CC100
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#define USB2_USB30_QSCRATCH_BASE 0x79B8800
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#define USB2_FEMTO_PHY_SEC_BASE 0x007C000
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struct usb_qscratch {
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u8 rsvd0[8];
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u32 *qscratch_cfg_reg;
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};
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check_member(usb_qscratch, qscratch_cfg_reg, 0x08);
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struct usb_usb2_phy_dig {
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u8 rsvd1[116];
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u32 utmi_ctrl5;
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u32 ctrl_common0;
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u32 ctrl_common1;
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u8 rsvd2[12];
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u32 phy_ctrl1;
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u32 phy_ctrl2;
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u8 rsvd3;
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u32 override_x0;
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u32 override_x1;
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u32 override_x2;
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u32 override_x3;
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u8 rsvd4[24];
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u32 tcsr_ctrl;
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u8 rsvd5[36];
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u32 refclk_ctrl;
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};
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check_member(usb_usb2_phy_dig, utmi_ctrl5, 0x74);
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check_member(usb_usb2_phy_dig, phy_ctrl1, 0x8C);
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check_member(usb_usb2_phy_dig, override_x0, 0x98);
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check_member(usb_usb2_phy_dig, tcsr_ctrl, 0xC0);
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check_member(usb_usb2_phy_dig, refclk_ctrl, 0xE8);
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struct usb_dwc3 {
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u32 sbuscfg0;
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u32 sbuscfg1;
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u32 txthrcfg;
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u32 rxthrcfg;
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u32 ctl;
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u32 pmsts;
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u32 sts;
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u32 uctl1;
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u32 snpsid;
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u32 gpio;
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u32 uid;
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u32 uctl;
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u64 buserraddr;
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u64 prtbimap;
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u8 reserved1[32];
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u32 dbgfifospace;
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u32 dbgltssm;
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u32 dbglnmcc;
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u32 dbgbmu;
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u32 dbglspmux;
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u32 dbglsp;
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u32 dbgepinfo0;
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u32 dbgepinfo1;
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u64 prtbimap_hs;
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u64 prtbimap_fs;
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u8 reserved2[112];
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u32 usb2phycfg;
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u8 reserved3[60];
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u32 usb2i2cctl;
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u8 reserved4[60];
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u32 usb2phyacc;
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u8 reserved5[60];
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u32 usb3pipectl;
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u8 reserved6[60];
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};
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check_member(usb_dwc3, usb3pipectl, 0x1c0);
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struct usb_dwc3_cfg {
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struct usb_dwc3 *usb_host_dwc3;
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struct usb_usb2_phy_dig *usb2_phy_dig;
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struct usb_qscratch *usb_qscratch_reg;
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u32 *usb2_phy_bcr;
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u32 *usb2_phy_por_bcr;
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u32 *usb3_bcr;
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struct usb_board_data *board_data;
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};
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static struct usb_dwc3_cfg usb_host_base[2] = {
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[HSUSB_SS_PORT_0] = {
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.usb_host_dwc3 = (void *)USB_HOST0_DWC3_BASE,
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.usb2_phy_dig = (void *)USB2_FEMTO_PHY_PRI_BASE,
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.usb2_phy_bcr = (void *)GCC_USB_HS_PHY_CFG_AHB_BCR,
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.usb2_phy_por_bcr = (void *)GCC_USB2A_PHY_BCR,
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.usb3_bcr = (void *)GCC_USB_30_BCR,
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.usb_qscratch_reg = (void *)USB3_USB30_QSCRATCH_BASE,
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},
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[HSUSB_HS_PORT_1] = {
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.usb_host_dwc3 = (void *)USB_HOST1_DWC3_BASE,
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.usb2_phy_dig = (void *)USB2_FEMTO_PHY_SEC_BASE,
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.usb2_phy_bcr = (void *)GCC_QUSB2_PHY_BCR,
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.usb2_phy_por_bcr = (void *)GCC_USB2_HS_PHY_ONLY_BCR,
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.usb3_bcr = (void *)GCC_USB_HS_BCR,
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.usb_qscratch_reg = (void *)USB2_USB30_QSCRATCH_BASE,
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},
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};
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void reset_usb(enum usb_port port)
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{
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struct usb_dwc3_cfg *dwc3 = &usb_host_base[port];
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/* Put Core in Reset */
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printk(BIOS_INFO, "Starting DWC3 reset for USB%d\n", port);
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/* Assert Core reset */
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clock_reset_bcr(dwc3->usb3_bcr, 1);
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}
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static void usb2_phy_override_phy_params(struct usb_dwc3_cfg *dwc3)
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{
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/* Override disconnect & squelch threshold values */
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write8(&dwc3->usb2_phy_dig->override_x0,
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dwc3->board_data->parameter_override_x0);
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/* Override HS transmitter Pre-emphasis values */
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write8(&dwc3->usb2_phy_dig->override_x1,
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dwc3->board_data->parameter_override_x1);
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/* Override HS transmitter Rise/Fall time values */
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write8(&dwc3->usb2_phy_dig->override_x2,
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dwc3->board_data->parameter_override_x2);
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/* Override FS/LS Source impedance values */
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write8(&dwc3->usb2_phy_dig->override_x3,
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dwc3->board_data->parameter_override_x3);
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}
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static void hs_usb_phy_init(struct usb_dwc3_cfg *dwc3)
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{
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write8(&dwc3->usb2_phy_dig->tcsr_ctrl, USB2PHY_TCSR_CTRL);
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write8(&dwc3->usb2_phy_dig->refclk_ctrl, USB2PHY_REFCLK_CTRL);
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write8(&dwc3->usb2_phy_dig->utmi_ctrl5, USB2PHY_UTMI_CTRL5);
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write8(&dwc3->usb2_phy_dig->override_x0, USB2PHY_PARAMETER_OVERRIDE_X0);
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write8(&dwc3->usb2_phy_dig->override_x1, USB2PHY_PARAMETER_OVERRIDE_X1);
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write8(&dwc3->usb2_phy_dig->override_x2, USB2PHY_PARAMETER_OVERRIDE_X2);
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write8(&dwc3->usb2_phy_dig->override_x3, USB2PHY_PARAMETER_OVERRIDE_X3);
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if (dwc3->board_data)
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/* Override board specific PHY tuning values */
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usb2_phy_override_phy_params(dwc3);
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write8(&dwc3->usb2_phy_dig->phy_ctrl1, USB2PHY_HS_PHY_CTRL1);
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write8(&dwc3->usb2_phy_dig->ctrl_common0, QUSB2PHY_HS_PHY_CTRL_COMMON0);
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write8(&dwc3->usb2_phy_dig->ctrl_common1, QUSB2PHY_HS_PHY_CTRL_COMMON1);
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write8(&dwc3->usb2_phy_dig->phy_ctrl2, USB2PHY_HS_PHY_CTRL2);
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udelay(20);
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write8(&dwc3->usb2_phy_dig->utmi_ctrl5, USB2PHY_UTMI_CTRL5_POR_CLEAR);
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write8(&dwc3->usb2_phy_dig->phy_ctrl2,
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USB2PHY_HS_PHY_CTRL2_SUSPEND_N_SEL);
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}
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static void setup_dwc3(struct usb_dwc3 *dwc3)
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{
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/* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */
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clrsetbits_le32(&dwc3->usb3pipectl,
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DWC3_GUSB3PIPECTL_DELAYP1TRANS,
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DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX);
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clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK |
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DWC3_GCTL_DISSCRAMBLE),
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DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG);
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/* configure controller in Host mode */
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clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)),
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DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST));
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printk(BIOS_INFO, "Configure USB in Host mode\n");
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}
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/* Initialization of DWC3 Core and PHY */
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void setup_usb_host(enum usb_port port, struct usb_board_data *board_data)
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{
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struct usb_dwc3_cfg *dwc3 = &usb_host_base[port];
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u32 val;
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printk(BIOS_INFO, "Setting up USB HOST%d controller.\n", port);
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dwc3->board_data = board_data;
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/* Clear core reset. */
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clock_reset_bcr(dwc3->usb3_bcr, 0);
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if (port == HSUSB_SS_PORT_0) {
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/* Set PHY reset. */
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setbits_le32(&dwc3->usb2_phy_bcr, BIT(1));
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udelay(15);
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/* Clear PHY reset. */
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clrbits_le32(&dwc3->usb2_phy_bcr, BIT(1));
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} else {
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clock_reset_bcr(dwc3->usb2_phy_bcr, 1);
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udelay(15);
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clock_reset_bcr(dwc3->usb2_phy_bcr, 0);
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}
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udelay(100);
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/* Initialize PHYs */
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hs_usb_phy_init(dwc3);
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if (port == HSUSB_SS_PORT_0) {
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/* Set PHY POR reset. */
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setbits_le32(&dwc3->usb2_phy_por_bcr, BIT(0));
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val = read8(&dwc3->usb2_phy_dig->ctrl_common0);
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val &= ~(0x4);
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write8(&dwc3->usb2_phy_dig->ctrl_common0, val);
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udelay(20);
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/* Clear PHY POR reset. */
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clrbits_le32(&dwc3->usb2_phy_por_bcr, BIT(0));
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} else {
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clock_reset_bcr(dwc3->usb2_phy_por_bcr, 1);
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val = read8(&dwc3->usb2_phy_dig->ctrl_common0);
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val &= ~(0x4);
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write8(&dwc3->usb2_phy_dig->ctrl_common0, val);
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udelay(20);
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clock_reset_bcr(dwc3->usb2_phy_por_bcr, 0);
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}
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udelay(100);
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setup_dwc3(dwc3->usb_host_dwc3);
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/*
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* Below sequence is used when dwc3 operates without
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* SSPHY and only HS/FS/LS modes are supported.
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*/
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/* Configure dwc3 to use UTMI clock as PIPE clock not present */
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setbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg,
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PIPE_UTMI_CLK_DIS);
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udelay(2);
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setbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg,
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PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
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udelay(3);
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clrbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg,
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PIPE_UTMI_CLK_DIS);
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printk(BIOS_INFO, "DWC3 and PHY setup finished\n");
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}
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