google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configuration
Add lpddr3-K4E6E304EB-2GB-1CH memory configuration for rialto. BUG=chrome-os-partner:56759 BRANCH=none TEST=Build Change-Id: I698fe450d48b64a06232aa44ecf91d688d9dc17a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d3edecdb135939c3264ab1b831e7821d3a3e0149 Original-Change-Id: I7dae9fd822abeff5b08de0ab9262e1817ac58531 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/380443 Original-Commit-Ready: Alexandru Stan <amstan@chromium.org> Original-Tested-by: Alexandru Stan <amstan@chromium.org> Original-Reviewed-by: Alexandru Stan <amstan@chromium.org> Original-Reviewed-by: Jonathan Dixon <joth@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16699 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -22,7 +22,7 @@
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static struct rk3288_sdram_params sdram_configs[] = {
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#include "sdram_inf/sdram-lpddr3-K4E8E304EE-1GB.inc" /* ram_code = 0000 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 0001 */
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#include "sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc"/* ram_code = 0001 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 0100 */
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@ -0,0 +1,90 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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{
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{
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{
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.rank = 0x2,
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.col = 0xA,
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.bk = 0x3,
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.bw = 0x2,
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.dbw = 0x2,
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.row_3_4 = 0x0,
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.cs0_row = 0xF,
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.cs1_row = 0xF
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},
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{
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.rank = 0x0,
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.col = 0x0,
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.bk = 0x0,
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.bw = 0x0,
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.dbw = 0x0,
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.row_3_4 = 0x0,
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.cs0_row = 0x0,
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.cs1_row = 0x0
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}
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},
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{
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.togcnt1u = 0x215,
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.tinit = 0xC8,
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.trsth = 0x0,
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.togcnt100n = 0x35,
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.trefi = 0x26,
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.tmrd = 0x2,
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.trfc = 0x70,
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.trp = 0x2000D,
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.trtw = 0x6,
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.tal = 0x0,
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.tcl = 0x8,
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.tcwl = 0x4,
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.tras = 0x17,
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.trc = 0x24,
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.trcd = 0xD,
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.trrd = 0x6,
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.trtp = 0x4,
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.twr = 0x8,
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.twtr = 0x4,
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.texsr = 0x76,
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.txp = 0x4,
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.txpdll = 0x0,
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.tzqcs = 0x30,
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.tzqcsi = 0x0,
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.tdqs = 0x1,
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.tcksre = 0x2,
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.tcksrx = 0x2,
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.tcke = 0x4,
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.tmod = 0x0,
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.trstl = 0x0,
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.tzqcl = 0xC0,
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.tmrr = 0x4,
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.tckesr = 0x8,
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.tdpd = 0x1F4
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},
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{
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.dtpr0 = 0x48D7DD93,
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.dtpr1 = 0x187008D8,
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.dtpr2 = 0x121076,
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.mr[0] = 0x0,
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.mr[1] = 0xC3,
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.mr[2] = 0x6,
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.mr[3] = 0x1
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},
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.noc_timing = 0x20D266A4,
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.noc_activate = 0x5B6,
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.ddrconfig = 3,
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.ddr_freq = 533*MHz,
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.dramtype = LPDDR3,
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.num_channels = 1,
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.stride = 22,
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.odt = 0
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},
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