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vendorcode/google/chromeos: Build CSE Board Reset in Romstage 

CSE Firmware Sync is being performed in romstage currently. But the CSE
board reset is not included as part of romstage. This causes the CSE
firmware sync to use global reset instead of EC assisted AP reset with
the old Cr50 Firmware version. Include the board specific CSE reset in
romstage.

BUG=b:171731175,b:177795247
BRANCH=dedede,volteer,puff
TEST=Ensured that the Drawlat boots to OS with both old(0.0.22) and
new(0.6.7) Cr50 FW versions.

Change-Id: I5e362271ffb68ffd5884279acd1ab0a462195a8a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49850
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Karthikeyan Ramasubramanian 2021-01-22 12:02:02 -07:00 committed by Tim Wawrzynczak
parent d736b1a607
commit dd4741c7bd
1 changed files with 2 additions and 0 deletions
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2
src/vendorcode/google/chromeos/Makefile.inc
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@ -10,6 +10,8 @@ ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c
ramstage-$(CONFIG_USE_SAR) += sar.c ramstage-$(CONFIG_USE_SAR) += sar.c
ramstage-$(CONFIG_CHROMEOS_DSM_CALIB) += dsm_calib.c ramstage-$(CONFIG_CHROMEOS_DSM_CALIB) += dsm_calib.c
ramstage-$(CONFIG_TPM_CR50) += cr50_enable_update.c ramstage-$(CONFIG_TPM_CR50) += cr50_enable_update.c
romstage-$(CONFIG_CHROMEOS_CSE_BOARD_RESET_OVERRIDE) += cse_board_reset.c
ramstage-$(CONFIG_CHROMEOS_CSE_BOARD_RESET_OVERRIDE) += cse_board_reset.c ramstage-$(CONFIG_CHROMEOS_CSE_BOARD_RESET_OVERRIDE) += cse_board_reset.c
bootblock-y += watchdog.c bootblock-y += watchdog.c