soc/amd/common/block: Add header file for eSPI register definitions
This change adds eSPI register definitions for I/O and MMIO decode using eSPI on AMD SoCs. Additionally, it also adds a macro to define the offset of ESPI MMIO base from SPI MMIO base. BUG=b:153675913 Change-Id: Ifb70ae0c63cc823334a1d851faf4dda6d1c1fc1a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#ifndef __AMDBLOCKS_ESPI_H__
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#define __AMDBLOCKS_ESPI_H__
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/* eSPI MMIO base lives at an offset of 0x10000 from the address in SPI BAR. */
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#define ESPI_OFFSET_FROM_BAR 0x10000
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#define ESPI_DECODE 0x40
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#define ESPI_DECODE_MMIO_RANGE_EN(range) (1 << (((range) & 3) + 12))
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#define ESPI_DECODE_IO_RANGE_EN(range) (1 << (((range) & 3) + 8))
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#define ESPI_DECODE_IO_0x80_EN (1 << 2)
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#define ESPI_DECODE_IO_0X60_0X64_EN (1 << 1)
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#define ESPI_DECODE_IO_0X2E_0X2F_EN (1 << 0)
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#define ESPI_IO_RANGE_BASE(range) (0x44 + ((range) & 3) * 2)
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#define ESPI_IO_RANGE_SIZE(range) (0x4c + ((range) & 3))
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#define ESPI_MMIO_RANGE_BASE(range) (0x50 + ((range) & 3) * 4)
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#define ESPI_MMIO_RANGE_SIZE(range) (0x60 + ((range) & 3) * 2)
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#define ESPI_GENERIC_IO_WIN_COUNT 4
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#define ESPI_GENERIC_IO_MAX_WIN_SIZE 0x100
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#define ESPI_GENERIC_MMIO_WIN_COUNT 4
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#define ESPI_GENERIC_MMIO_MAX_WIN_SIZE 0x10000
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#endif /* __AMDBLOCKS_ESPI_H__ */
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