GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Following patch fixes the retrain/reset sequence which caused problem with some 

nVidia cards. The enable link should be enough, retrain is done there.

Tested on my system.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Rudolf Marek 2008-03-15 00:19:34 +00:00
parent 1ce63770a1
commit dd52e17448
1 changed files with 0 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
src/southbridge/via/k8t890/k8t890_pcie.c
View File

@ -41,8 +41,6 @@ static void peg_init(struct device *dev)
* pci_write_config8(dev, 0xe2, 0x0);
* pci_write_config8(dev, 0xe3, 0x92);
*/
/* Disable scrambling bit 6 to 1. */
pci_write_config8(dev, 0xc0, 0x43);
/* Set replay timer limit. */
pci_write_config8(dev, 0xb1, 0xf0);
@ -62,18 +60,6 @@ static void peg_init(struct device *dev)
reg = pci_read_config8(dev, 0x50);
pci_write_config8(dev, 0x50, reg & ~0x10);
/* Retrain link. */
reg = pci_read_config8(dev, 0x50);
pci_write_config8(dev, 0x50, reg | 0x20);
reg = pci_read_config8(dev, 0x3e);
reg |= 0x40; /* Bus reset. */
pci_write_config8(dev, 0x3e, reg);
reg = pci_read_config8(dev, 0x3e);
reg &= ~0x40; /* Clear reset. */
pci_write_config8(dev, 0x3e, reg);
dump_south(dev);
}
@ -97,18 +83,6 @@ static void pcie_init(struct device *dev)
reg = pci_read_config8(dev, 0x50);
pci_write_config8(dev, 0x50, reg & ~0x10);
/* Retrain. */
reg = pci_read_config8(dev, 0x50);
pci_write_config8(dev, 0x50, reg | 0x20);
reg = pci_read_config8(dev, 0x3e);
reg |= 0x40; /* Bus reset. */
pci_write_config8(dev, 0x3e, reg);
reg = pci_read_config8(dev, 0x3e);
reg &= ~0x40; /* Clear reset. */
pci_write_config8(dev, 0x3e, reg);
dump_south(dev);
}