soc/intel/broadwell: Use common early SMBus code
Disabling interrupts and clearing errors was being done twice, once in the `smbus_enable_iobar` reg-script, and another in `enable_smbus`. Change-Id: I58558996bd693b302764965a5bed8b96db363833 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -17,6 +17,7 @@ config CPU_SPECIFIC_OPTIONS
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select SUPPORT_CPU_UCODE_IN_CBFS
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select HAVE_SMI_HANDLER
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select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
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select SOUTHBRIDGE_INTEL_COMMON_RESET
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select SOUTHBRIDGE_INTEL_COMMON_RTC
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select SOUTHBRIDGE_INTEL_COMMON_SMBUS
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@ -5,6 +5,5 @@ romstage-y += power_state.c
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romstage-y += raminit.c
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romstage-y += report_platform.c
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romstage-y += romstage.c
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romstage-y += smbus.c
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romstage-y += systemagent.c
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romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
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@ -1,35 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/pci_def.h>
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#include <device/smbus_host.h>
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#include <reg_script.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/smbus.h>
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#include <soc/romstage.h>
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static const struct reg_script smbus_init_script[] = {
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/* Set SMBUS I/O base address */
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REG_PCI_WRITE32(SMB_BASE, SMBUS_BASE_ADDRESS | 1),
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/* Set SMBUS enable */
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REG_PCI_WRITE8(HOSTC, HST_EN),
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/* Enable I/O access */
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REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO),
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/* Disable interrupts */
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REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0),
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/* Clear errors */
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REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff),
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/* Indicate the end of this array by REG_SCRIPT_END */
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REG_SCRIPT_END,
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};
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uintptr_t smbus_base(void)
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{
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return SMBUS_BASE_ADDRESS;
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}
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int smbus_enable_iobar(uintptr_t base)
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{
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reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script);
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return 0;
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}
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