his patch fixes the CAS map for -.5 and -1 CAS settings. The -.5 setting should only shift the mask one bit, not two.
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -151,7 +151,7 @@ static void checkDDRMax(void)
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}
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/* I don't think you need this check.
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if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0){
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if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0){
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print_debug("DIMM overclocked. Check GeodeLink Speed\n");
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POST_CODE(POST_PLL_MEM_FAIL);
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__asm__ __volatile__("hlt\n");
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@ -231,7 +231,7 @@ static void setCAS(void)
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;* Destroys: We really use everything !
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;*****************************************************************************/
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uint16_t glspeed, dimm_speed;
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uint8_t spd_byte, casmap0, casmap1;
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uint8_t spd_byte, casmap0, casmap1, casmap_shift;
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msr_t msr;
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glspeed = GeodeLinkSpeed();
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@ -246,25 +246,24 @@ static void setCAS(void)
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dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) +
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(spd_byte & 0x0F)));
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if (dimm_speed >= glspeed) {
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casmap_shift = 1; /* -.5 is a shift of 1 */
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/* IF -1 timing is supported, check -1 timing > GeodeLink */
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spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD);
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if (spd_byte != 0) {
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/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
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dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
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if (dimm_speed <= glspeed) {
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/* set we can use -.5 timing but not -1 */
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spd_byte = 31 - __builtin_clz((uint32_t) casmap0);
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/* just want bits in the lower byte since we have to cast to a 32 */
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casmap0 &= 0xFF << (--spd_byte);
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if (dimm_speed >= glspeed) {
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casmap_shift = 2; /* -1 is a shift of 2 */
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}
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} /*MIN_CYCLE_10 !=0 */
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} /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */
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} else {
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/* Timing_05 < GLspeed, can't use -.5 or -1 timing */
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spd_byte = 31 - __builtin_clz((uint32_t) casmap0);
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/* just want bits in the lower byte since we have to cast to a 32 */
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casmap0 &= 0xFF << (spd_byte);
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casmap_shift = 0;
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}
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} /*MIN_CYCLE_05 !=0 */
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} /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */
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/* set the casmap based on the shift to limit possible CAS settings */
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spd_byte = 31 - __builtin_clz((uint32_t) casmap0);
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/* just want bits in the lower byte since we have to cast to a 32 */
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casmap0 &= 0xFF << (spd_byte - casmap_shift);
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} else { /* No DIMM */
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casmap0 = 0;
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}
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@ -278,25 +277,25 @@ static void setCAS(void)
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/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
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dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
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if (dimm_speed >= glspeed) {
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casmap_shift = 1; /* -.5 is a shift of 1 */
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/* IF -1 timing is supported, check -1 timing > GeodeLink */
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spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_3RD);
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if (spd_byte != 0) {
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/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
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dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
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if (dimm_speed <= glspeed) {
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/* set we can use -.5 timing but not -1 */
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spd_byte = 31 - __builtin_clz((uint32_t) casmap1);
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/* just want bits in the lower byte since we have to cast to a 32 */
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casmap1 &= 0xFF << (--spd_byte);
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if (dimm_speed >= glspeed) {
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casmap_shift = 2; /* -1 is a shift of 2 */
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}
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} /*MIN_CYCLE_10 !=0 */
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/* note that the -1 result doesn't need to change the available CAS map */
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} /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */
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} else {
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/* Timing_05 < GLspeed, can't use -.5 or -1 timing */
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spd_byte = 31 - __builtin_clz((uint32_t) casmap1);
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/* just want bits in the lower byte since we have to cast to a 32 */
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casmap1 &= 0xFF << (spd_byte);
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casmap_shift = 0;
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}
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} /*MIN_CYCLE_05 !=0 */
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} /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */
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/* set the casmap based on the shift to limit possible CAS settings */
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spd_byte = 31 - __builtin_clz((uint32_t) casmap1);
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/* just want bits in the lower byte since we have to cast to a 32 */
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casmap1 &= 0xFF << (spd_byte - casmap_shift);
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} else { /* No DIMM */
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casmap1 = 0;
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}
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