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nb/intel/ironlake/ironlake.h: Clean up 

Align values and drop copy-pasted, wrong and unused definitions.

Tested with BUILD_TIMELESS=1, packardbell/ms2290 remains identical.

Change-Id: I44f96982c8a38e1933cd78a976e18a8a11fb4096
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Angel Pons 2020-06-22 17:21:23 +02:00 committed by Patrick Georgi
parent b639707056
commit dd6a3d841b
1 changed files with 50 additions and 73 deletions
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35
src/northbridge/intel/ironlake/ironlake.h
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@ -28,7 +28,7 @@
#define D0F0_DMIBAR_LO 0x68 #define D0F0_DMIBAR_LO 0x68
#define D0F0_DMIBAR_HI 0x6c #define D0F0_DMIBAR_HI 0x6c
#define D0F0_PMBASE 0x78 #define D0F0_PMBASE 0x78
#define QPD0F1_PAM(x) (0x40+(x)) /* 0-6*/ #define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */
#define D0F0_REMAPBASE 0x98 #define D0F0_REMAPBASE 0x98
#define D0F0_REMAPLIMIT 0x9a #define D0F0_REMAPLIMIT 0x9a
#define D0F0_TOM 0xa0 #define D0F0_TOM 0xa0
@ -56,23 +56,6 @@
#define IRONLAKE_DESKTOP 1 #define IRONLAKE_DESKTOP 1
#define IRONLAKE_SERVER 2 #define IRONLAKE_SERVER 2
/* Device ID for SandyBridge and IvyBridge */
#define BASE_REV_SNB 0x00
#define BASE_REV_IVB 0x50
#define BASE_REV_MASK 0x50
/* SandyBridge CPU stepping */
#define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */
#define SNB_STEP_D1 (BASE_REV_SNB + 6)
#define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */
/* IvyBridge CPU stepping */
#define IVB_STEP_A0 (BASE_REV_IVB + 0)
#define IVB_STEP_B0 (BASE_REV_IVB + 2)
#define IVB_STEP_C0 (BASE_REV_IVB + 4)
#define IVB_STEP_K0 (BASE_REV_IVB + 5)
#define IVB_STEP_D0 (BASE_REV_IVB + 6)
/* Northbridge BARs */ /* Northbridge BARs */
#ifndef __ACPI__ #ifndef __ACPI__
#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ #define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */
@ -117,17 +100,14 @@
#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and))
#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or))
#define MCHBAR8_AND_OR(x, and, or) \
(MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or))
#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and))
#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or))
#define MCHBAR16_AND_OR(x, and, or) \
(MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or))
#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and))
#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or))
#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or))
#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) #define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or))
#define MCHBAR32_AND_OR(x, and, or) \ #define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or))
(MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) #define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or))
#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
/* /*
* EPBAR - Egress Port Root Complex Register Block * EPBAR - Egress Port Root Complex Register Block
*/ */
@ -199,9 +179,6 @@
#ifndef __ASSEMBLER__ #ifndef __ASSEMBLER__
#define PCI_DEVICE_ID_SB 0x0104
#define PCI_DEVICE_ID_IB 0x0154
void intel_ironlake_finalize_smm(void); void intel_ironlake_finalize_smm(void);
int bridge_silicon_revision(void); int bridge_silicon_revision(void);