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mb/asrock/b85m_pro4: Factor out common MRC settings 

These settings are the same on all boards. Since the other boards
currently overwrite the struct contents, it doesn't make a difference.
To ease review, the same settings will be dropped from other boards in
separate commits, one board at a time.

Change-Id: I500b7a1d7d97c6976e0c7c10ca491d3875cae22b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
This commit is contained in:
Angel Pons 2020-07-03 18:19:29 +02:00
parent 45f448f4a4
commit dd7470cb7e
2 changed files with 56 additions and 46 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

90
src/mainboard/asrock/b85m_pro4/romstage.c
View File

@ -23,52 +23,50 @@ void mainboard_config_rcba(void)
void mainboard_fill_pei_data(struct pei_data *pei_data) void mainboard_fill_pei_data(struct pei_data *pei_data)
{ {
struct pei_data mainboard_pei_data = { pei_data->system_type = 1; /* Desktop/Server */
.pei_version = PEI_VERSION, pei_data->spd_addresses[0] = 0xa0;
.mchbar = (uintptr_t)DEFAULT_MCHBAR, pei_data->spd_addresses[1] = 0xa2;
.dmibar = (uintptr_t)DEFAULT_DMIBAR, pei_data->spd_addresses[2] = 0xa4;
.epbar = DEFAULT_EPBAR, pei_data->spd_addresses[3] = 0xa6;
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS, pei_data->ec_present = 0;
.smbusbar = SMBUS_IO_BASE, pei_data->gbe_enable = 1;
.hpet_address = HPET_ADDR, /*
.rcba = (uintptr_t)DEFAULT_RCBA, * 0 = leave channel enabled
.pmbase = DEFAULT_PMBASE, * 1 = disable dimm 0 on channel
.gpiobase = DEFAULT_GPIOBASE, * 2 = disable dimm 1 on channel
.temp_mmio_base = 0xfed08000, * 3 = disable dimm 0+1 on channel
.system_type = 1, /* desktop/server */ */
.tseg_size = CONFIG_SMM_TSEG_SIZE, pei_data->dimm_channel0_disabled = 0;
.spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, pei_data->dimm_channel1_disabled = 0;
.ec_present = 0, pei_data->max_ddr3_freq = 1600;
.gbe_enable = 1,
.dimm_channel0_disabled = 0, struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
.dimm_channel1_disabled = 0, /* Length, Enable, OCn#, Location */
.max_ddr3_freq = 1600, { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
.usb2_ports = { { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
/* Length, Enable, OCn#, Location */ { 0x0040, 1, 1, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL }, { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL }, { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 1, USB_PORT_BACK_PANEL }, { 0x0040, 1, 2, USB_PORT_BACK_PANEL },
{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 2, USB_PORT_BACK_PANEL }, { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 3, USB_PORT_BACK_PANEL }, { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 3, USB_PORT_BACK_PANEL }, { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 4, USB_PORT_BACK_PANEL }, { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 4, USB_PORT_BACK_PANEL }, { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 5, USB_PORT_BACK_PANEL }, { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 5, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
},
.usb3_ports = {
{ 1, 0 },
{ 1, 0 },
{ 1, 1 },
{ 1, 1 },
{ 1, 2 },
{ 1, 2 },
},
}; };
*pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */ struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = {
{ 1, 0 },
{ 1, 0 },
{ 1, 1 },
{ 1, 1 },
{ 1, 2 },
{ 1, 2 },
};
memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports));
memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports));
} }

12
src/northbridge/intel/haswell/romstage.c
View File

@ -29,6 +29,18 @@ void mainboard_romstage_entry(void)
int wake_from_s3; int wake_from_s3;
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.hpet_address = HPET_ADDR,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.temp_mmio_base = 0xfed08000,
.tseg_size = CONFIG_SMM_TSEG_SIZE,
}; };
mainboard_fill_pei_data(&pei_data); mainboard_fill_pei_data(&pei_data);