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soc/amd/stoneyridge: Move BERT into a cbmem region 

This removes the need to align BERT so that TSEG remains aligned.

Change-Id: I21b55a87838dcb4bd4099f051ba0a011a4d41eea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans 2022-05-23 16:06:06 +02:00 committed by Felix Held
parent 743627fba2
commit dd7ec09155
2 changed files with 17 additions and 18 deletions
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8
src/soc/amd/stoneyridge/Kconfig
View File

@ -373,4 +373,12 @@ config DISABLE_KEYBOARD_RESET_PIN
functionality isn't disabled, configuring it as an output and driving functionality isn't disabled, configuring it as an output and driving
it as 0 will cause a reset. it as 0 will cause a reset.
config ACPI_BERT_SIZE
hex
default 0x100000 if ACPI_BERT
default 0x0
help
Specify the amount of DRAM reserved for gathering the data used to
generate the ACPI table.
endif # SOC_AMD_STONEYRIDGE endif # SOC_AMD_STONEYRIDGE

27
src/soc/amd/stoneyridge/memmap.c
View File

@ -13,24 +13,16 @@
#include <soc/iomap.h> #include <soc/iomap.h>
#include <amdblocks/biosram.h> #include <amdblocks/biosram.h>
#if CONFIG(ACPI_BERT)
#if CONFIG_SMM_TSEG_SIZE == 0x0
#define BERT_REGION_MAX_SIZE 0x100000
#else
/* SMM_TSEG_SIZE must stay on a boundary appropriate for its granularity */
#define BERT_REGION_MAX_SIZE CONFIG_SMM_TSEG_SIZE
#endif
#else
#define BERT_REGION_MAX_SIZE 0
#endif
void bert_reserved_region(void **start, size_t *size) void bert_reserved_region(void **start, size_t *size)
{ {
if (CONFIG(ACPI_BERT)) if (!CONFIG(ACPI_BERT)) {
*start = cbmem_top();
else
*start = NULL; *start = NULL;
*size = BERT_REGION_MAX_SIZE; *size = 0;
} else {
*start = cbmem_add(CBMEM_ID_ACPI_BERT, CONFIG_ACPI_BERT_SIZE);
*size = CONFIG_ACPI_BERT_SIZE;
}
printk(BIOS_INFO, "Reserved BERT region base: %p, size: 0x%zx\n", *start, *size);
} }
void *cbmem_top_chipset(void) void *cbmem_top_chipset(void)
@ -42,13 +34,12 @@ void *cbmem_top_chipset(void)
/* 8MB alignment to keep MTRR usage low */ /* 8MB alignment to keep MTRR usage low */
return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() return (void *)ALIGN_DOWN(restore_top_of_low_cacheable()
- CONFIG_SMM_TSEG_SIZE - CONFIG_SMM_TSEG_SIZE, 8*MiB);
- BERT_REGION_MAX_SIZE, 8*MiB);
} }
static uintptr_t smm_region_start(void) static uintptr_t smm_region_start(void)
{ {
return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE; return (uintptr_t)cbmem_top();
} }
static size_t smm_region_size(void) static size_t smm_region_size(void)