sb/intel/i82801jx: Move `acpi_fill_fadt` to fadt.c
At least i82801ix does this. Change-Id: Ic555ab17c2eca0399938d2842ca51628899c1544 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42637 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
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@ -6,6 +6,7 @@ bootblock-y += bootblock.c
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bootblock-y += early_init.c
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bootblock-y += early_init.c
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ramstage-y += i82801jx.c
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ramstage-y += i82801jx.c
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ramstage-y += fadt.c
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ramstage-y += pci.c
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ramstage-y += pci.c
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ramstage-y += lpc.c
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ramstage-y += lpc.c
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ramstage-y += pcie.c
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ramstage-y += pcie.c
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@ -0,0 +1,126 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <string.h>
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#include <device/pci_ops.h>
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#include <acpi/acpi.h>
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#include <cpu/x86/smm.h>
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#include <version.h>
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#include "chip.h"
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void acpi_fill_fadt(acpi_fadt_t *fadt)
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{
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struct device *dev = pcidev_on_root(0x1f, 0);
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struct southbridge_intel_i82801jx_config *chip = dev->chip_info;
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u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
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fadt->pm1a_evt_blk = pmbase;
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fadt->pm1b_evt_blk = 0x0;
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fadt->pm1a_cnt_blk = pmbase + 0x4;
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fadt->pm1b_cnt_blk = 0x0;
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fadt->pm2_cnt_blk = pmbase + 0x50;
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fadt->pm_tmr_blk = pmbase + 0x8;
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fadt->gpe0_blk = pmbase + 0x20;
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fadt->gpe1_blk = 0;
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fadt->pm1_evt_len = 4;
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fadt->pm1_cnt_len = 2;
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fadt->pm2_cnt_len = 1;
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fadt->pm_tmr_len = 4;
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fadt->gpe0_blk_len = 16;
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fadt->gpe1_blk_len = 0;
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fadt->gpe1_base = 0;
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fadt->reset_reg.space_id = 1;
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fadt->reset_reg.bit_width = 8;
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fadt->reset_reg.bit_offset = 0;
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fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->reset_reg.addrl = 0xcf9;
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fadt->reset_reg.addrh = 0;
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fadt->reset_value = 6;
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fadt->x_pm1a_evt_blk.space_id = 1;
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fadt->x_pm1a_evt_blk.bit_width = 32;
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fadt->x_pm1a_evt_blk.bit_offset = 0;
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fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_pm1a_evt_blk.addrl = pmbase;
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fadt->x_pm1a_evt_blk.addrh = 0x0;
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fadt->x_pm1b_evt_blk.space_id = 0;
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fadt->x_pm1b_evt_blk.bit_width = 0;
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fadt->x_pm1b_evt_blk.bit_offset = 0;
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fadt->x_pm1b_evt_blk.access_size = 0;
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fadt->x_pm1b_evt_blk.addrl = 0x0;
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fadt->x_pm1b_evt_blk.addrh = 0x0;
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fadt->x_pm1a_cnt_blk.space_id = 1;
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fadt->x_pm1a_cnt_blk.bit_width = 16;
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fadt->x_pm1a_cnt_blk.bit_offset = 0;
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fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
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fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
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fadt->x_pm1a_cnt_blk.addrh = 0x0;
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fadt->x_pm1b_cnt_blk.space_id = 0;
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fadt->x_pm1b_cnt_blk.bit_width = 0;
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fadt->x_pm1b_cnt_blk.bit_offset = 0;
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fadt->x_pm1b_cnt_blk.access_size = 0;
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fadt->x_pm1b_cnt_blk.addrl = 0x0;
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fadt->x_pm1b_cnt_blk.addrh = 0x0;
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fadt->x_pm2_cnt_blk.space_id = 1;
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fadt->x_pm2_cnt_blk.bit_width = 8;
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fadt->x_pm2_cnt_blk.bit_offset = 0;
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fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
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fadt->x_pm2_cnt_blk.addrh = 0x0;
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fadt->x_pm_tmr_blk.space_id = 1;
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fadt->x_pm_tmr_blk.bit_width = 32;
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fadt->x_pm_tmr_blk.bit_offset = 0;
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fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
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fadt->x_pm_tmr_blk.addrh = 0x0;
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fadt->x_gpe0_blk.space_id = 1;
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fadt->x_gpe0_blk.bit_width = 128;
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fadt->x_gpe0_blk.bit_offset = 0;
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fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->x_gpe0_blk.addrl = pmbase + 0x20;
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fadt->x_gpe0_blk.addrh = 0x0;
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fadt->x_gpe1_blk.space_id = 0;
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fadt->x_gpe1_blk.bit_width = 0;
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fadt->x_gpe1_blk.bit_offset = 0;
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fadt->x_gpe1_blk.access_size = 0;
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fadt->x_gpe1_blk.addrl = 0x0;
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fadt->x_gpe1_blk.addrh = 0x0;
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fadt->day_alrm = 0xd;
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fadt->mon_alrm = 0x00;
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fadt->century = 0x32;
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fadt->sci_int = 0x9;
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if (permanent_smi_handler()) {
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fadt->smi_cmd = APM_CNT;
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fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
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fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
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fadt->cst_cnt = APM_CNT_CST_CONTROL;
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fadt->pstate_cnt = APM_CNT_PST_CONTROL;
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}
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fadt->p_lvl2_lat = 1;
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fadt->p_lvl3_lat = chip->c3_latency;
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fadt->flush_size = 0;
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fadt->flush_stride = 0;
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fadt->duty_offset = 1;
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if (chip->p_cnt_throttling_supported)
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fadt->duty_width = 3;
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else
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fadt->duty_width = 0;
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fadt->iapc_boot_arch = 0x03;
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fadt->flags = (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED
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| ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE
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| ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_RESET_REGISTER
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| ACPI_FADT_C2_MP_SUPPORTED);
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if (chip->docking_supported)
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fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
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}
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@ -425,124 +425,6 @@ unsigned long acpi_fill_madt(unsigned long current)
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return current;
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return current;
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}
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}
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void acpi_fill_fadt(acpi_fadt_t *fadt)
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{
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struct device *dev = pcidev_on_root(0x1f, 0);
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config_t *chip = dev->chip_info;
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u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
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fadt->pm1a_evt_blk = pmbase;
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fadt->pm1b_evt_blk = 0x0;
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fadt->pm1a_cnt_blk = pmbase + 0x4;
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fadt->pm1b_cnt_blk = 0x0;
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fadt->pm2_cnt_blk = pmbase + 0x50;
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fadt->pm_tmr_blk = pmbase + 0x8;
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fadt->gpe0_blk = pmbase + 0x20;
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fadt->gpe1_blk = 0;
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fadt->pm1_evt_len = 4;
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fadt->pm1_cnt_len = 2;
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fadt->pm2_cnt_len = 1;
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fadt->pm_tmr_len = 4;
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fadt->gpe0_blk_len = 16;
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fadt->gpe1_blk_len = 0;
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fadt->gpe1_base = 0;
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fadt->reset_reg.space_id = 1;
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fadt->reset_reg.bit_width = 8;
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fadt->reset_reg.bit_offset = 0;
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fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->reset_reg.addrl = 0xcf9;
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fadt->reset_reg.addrh = 0;
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fadt->reset_value = 6;
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fadt->x_pm1a_evt_blk.space_id = 1;
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fadt->x_pm1a_evt_blk.bit_width = 32;
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fadt->x_pm1a_evt_blk.bit_offset = 0;
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fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_pm1a_evt_blk.addrl = pmbase;
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fadt->x_pm1a_evt_blk.addrh = 0x0;
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fadt->x_pm1b_evt_blk.space_id = 0;
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fadt->x_pm1b_evt_blk.bit_width = 0;
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fadt->x_pm1b_evt_blk.bit_offset = 0;
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fadt->x_pm1b_evt_blk.access_size = 0;
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fadt->x_pm1b_evt_blk.addrl = 0x0;
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fadt->x_pm1b_evt_blk.addrh = 0x0;
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fadt->x_pm1a_cnt_blk.space_id = 1;
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fadt->x_pm1a_cnt_blk.bit_width = 16;
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fadt->x_pm1a_cnt_blk.bit_offset = 0;
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fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
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fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
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fadt->x_pm1a_cnt_blk.addrh = 0x0;
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fadt->x_pm1b_cnt_blk.space_id = 0;
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fadt->x_pm1b_cnt_blk.bit_width = 0;
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fadt->x_pm1b_cnt_blk.bit_offset = 0;
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fadt->x_pm1b_cnt_blk.access_size = 0;
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fadt->x_pm1b_cnt_blk.addrl = 0x0;
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fadt->x_pm1b_cnt_blk.addrh = 0x0;
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fadt->x_pm2_cnt_blk.space_id = 1;
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fadt->x_pm2_cnt_blk.bit_width = 8;
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fadt->x_pm2_cnt_blk.bit_offset = 0;
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fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
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fadt->x_pm2_cnt_blk.addrh = 0x0;
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fadt->x_pm_tmr_blk.space_id = 1;
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fadt->x_pm_tmr_blk.bit_width = 32;
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fadt->x_pm_tmr_blk.bit_offset = 0;
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fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
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fadt->x_pm_tmr_blk.addrh = 0x0;
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fadt->x_gpe0_blk.space_id = 1;
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fadt->x_gpe0_blk.bit_width = 128;
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fadt->x_gpe0_blk.bit_offset = 0;
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fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->x_gpe0_blk.addrl = pmbase + 0x20;
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fadt->x_gpe0_blk.addrh = 0x0;
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fadt->x_gpe1_blk.space_id = 0;
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fadt->x_gpe1_blk.bit_width = 0;
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fadt->x_gpe1_blk.bit_offset = 0;
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fadt->x_gpe1_blk.access_size = 0;
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fadt->x_gpe1_blk.addrl = 0x0;
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fadt->x_gpe1_blk.addrh = 0x0;
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fadt->day_alrm = 0xd;
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fadt->mon_alrm = 0x00;
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fadt->century = 0x32;
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fadt->sci_int = 0x9;
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if (permanent_smi_handler()) {
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fadt->smi_cmd = APM_CNT;
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fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
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fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
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fadt->cst_cnt = APM_CNT_CST_CONTROL;
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fadt->pstate_cnt = APM_CNT_PST_CONTROL;
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}
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fadt->p_lvl2_lat = 1;
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fadt->p_lvl3_lat = chip->c3_latency;
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fadt->flush_size = 0;
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fadt->flush_stride = 0;
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fadt->duty_offset = 1;
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if (chip->p_cnt_throttling_supported)
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fadt->duty_width = 3;
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else
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fadt->duty_width = 0;
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fadt->iapc_boot_arch = 0x03;
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fadt->flags = (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED
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| ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE
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| ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_RESET_REGISTER
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| ACPI_FADT_C2_MP_SUPPORTED);
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if (chip->docking_supported)
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fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
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}
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static void i82801jx_lpc_read_resources(struct device *dev)
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static void i82801jx_lpc_read_resources(struct device *dev)
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{
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{
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int i, io_index = 0;
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int i, io_index = 0;
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