mainboard/google/reef: indicate dual rank LPDDR4 skus
The 16Gb devices use two ranks per channel within the DRAM module. However, the density settings are really on a per rank basis so indicate dual rank with a device density of 8Gb. BUG=chrome-os-partner:55446 Change-Id: Ib5dba6f9ed248750d68b726996c71def9b75961e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15772 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -71,11 +71,17 @@ static const struct lpddr4_swizzle_cfg board_swizzle = {
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#define PROTO_SKU 15
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static const struct lpddr4_sku skus[] = {
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/* K4F6E304HB-MGCJ - both logical channels */
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/*
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* K4F6E304HB-MGCJ - both logical channels While the parts
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* are listed at 16Gb there are 2 ranks per channel so indicate
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* the deneisty as 8Gb per rank.
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*/
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[0] = {
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.speed = LP4_SPEED_2400,
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.ch0_density = LP4_16Gb_DENSITY,
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.ch1_density = LP4_16Gb_DENSITY,
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.ch0_density = LP4_8Gb_DENSITY,
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.ch1_density = LP4_8Gb_DENSITY,
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.ch0_dual_rank = 1,
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.ch1_dual_rank = 1,
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},
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/* K4F8E304HB-MGCJ - both logical channels */
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[1] = {
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@ -83,13 +89,19 @@ static const struct lpddr4_sku skus[] = {
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.ch0_density = LP4_8Gb_DENSITY,
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.ch1_density = LP4_8Gb_DENSITY,
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},
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/* MT53B512M32D2NP-062WT:C - both logical channels */
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/*
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* MT53B512M32D2NP-062WT:C - both logical channels. While the parts
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* are listed at 16Gb there are 2 ranks per channel so indicate
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* the deneisty as 8Gb per rank.
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*/
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[2] = {
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.speed = LP4_SPEED_2400,
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.ch0_density = LP4_16Gb_DENSITY,
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.ch1_density = LP4_16Gb_DENSITY,
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/* MT53B256M32D1NP-062 WT:C - both logical channels */
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.ch0_density = LP4_8Gb_DENSITY,
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.ch1_density = LP4_8Gb_DENSITY,
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.ch0_dual_rank = 1,
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.ch1_dual_rank = 1,
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},
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/* MT53B256M32D1NP-062 WT:C - both logical channels */
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[3] = {
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.speed = LP4_SPEED_2400,
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.ch0_density = LP4_8Gb_DENSITY,
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