soc/mediatek/mt8195: add SPM loader
This patch adds support for loading SPM firmware from CBFS to SPM SRAM. SPM needs its own firmware to enable SPM suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. TEST=program counter of SPM is correct value after booting up. Change-Id: Ia0f9b9f86e44b293c1cc47213946304c64aea75e Signed-off-by: Dawei Chien <dawei.chien@mediatek.com> Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55140 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Dawei Chien
Hung-Te Lin
parent
80373767ed
commit
dd8f241292
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@ -25,6 +25,12 @@ config MCUPM_FIRMWARE
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help
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The file name of the MediaTek MCUPM firmware.
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config SPM_FIRMWARE
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string
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default "spm_firmware.bin"
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help
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The file name of the MediaTek SPM firmware.
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config SSPM_FIRMWARE
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string
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default "sspm.bin"
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@ -55,6 +55,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c
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ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
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ramstage-y += soc.c
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ramstage-y += ../common/sspm.c
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ramstage-y += ../common/spm.c spm.c
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ramstage-y += ../common/timer.c timer.c
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ramstage-y += ../common/uart.c
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ramstage-y += ../common/ufs.c
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@ -68,7 +69,8 @@ MT8195_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8195
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mcu-firmware-files := \
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$(CONFIG_MCUPM_FIRMWARE) \
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$(CONFIG_SSPM_FIRMWARE)
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$(CONFIG_SSPM_FIRMWARE) \
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$(CONFIG_SPM_FIRMWARE)
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$(foreach fw, $(call strip_quotes,$(mcu-firmware-files)), \
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$(eval $(fw)-file := $(MT8195_BLOB_DIR)/$(fw)) \
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@ -3,13 +3,413 @@
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#ifndef SOC_MEDIATEK_MT8195_SPM_H
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#define SOC_MEDIATEK_MT8195_SPM_H
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#include <device/mmio.h>
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#include <soc/addressmap.h>
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#include <soc/mtcmos.h>
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#include <stdint.h>
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#include <types.h>
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/* SPM READ/WRITE CFG */
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#define SPM_PROJECT_CODE 0xb16
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#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16)
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#define SPM_PROJECT_CODE 0xb16
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#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16)
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/* POWERON_CONFIG_EN (0x10006000+0x000) */
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#define BCLK_CG_EN_LSB (1U << 0)
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/* SPM_CLK_CON (0x10006000+0x00C) */
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DEFINE_BIT(REG_SYSCLK1_SRC_MD2_SRCCLKENA, 28)
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/* PCM_CON0 (0x10006000+0x018) */
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#define PCM_CK_EN_LSB (1U << 2)
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#define PCM_SW_RESET_LSB (1U << 15)
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/* PCM_CON1 (0x10006000+0x01C) */
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#define RG_IM_SLAVE_LSB (1U << 0)
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#define RG_AHBMIF_APBEN_LSB (1U << 3)
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#define RG_PCM_TIMER_EN_LSB (1U << 5)
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#define SPM_EVENT_COUNTER_CLR_LSB (1U << 6)
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#define RG_PCM_WDT_WAKE_LSB (1U << 9)
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#define REG_SPM_SRAM_ISOINT_B_LSB (1U << 11)
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#define REG_EVENT_LOCK_EN_LSB (1U << 12)
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#define REG_MD32_APB_INTERNAL_EN_LSB (1U << 14)
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/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0D0) */
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#define SPM_WAKEUP_EVENT_MASK_BIT0 (1U << 0)
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#define SPM_WAKEUP_EVENT_MASK_CSYSPWREQ_B (1U << 11)
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/* DDR_EN_DBC_CON1 (0x10006000+0x0EC) */
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#define REG_ALL_DDR_EN_DBC_EN_LSB (1U << 0)
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/* SPM_DVFS_MISC (0x10006000+0x4AC) */
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DEFINE_BIT(SPM_DVFS_FORCE_ENABLE_LSB, 2)
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DEFINE_BIT(SPM_DVFSRC_ENABLE_LSB, 4)
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/* SPM_SW_FLAG_0 (0x10006000+0x600) */
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#define SPM_FLAG_DISABLE_VCORE_DVS (1U << 3)
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#define SPM_FLAG_DISABLE_VCORE_DFS (1U << 4)
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#define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10)
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/* SYS_TIMER_CON (0x10006000+0x98C) */
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DEFINE_BIT(SYS_TIMER_START_EN_LSB, 0)
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/* MD32PCM_CFGREG_SW_RSTN (0x10006000+0xA00) */
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DEFINE_BIT(MD32PCM_CFGREG_SW_RSTN_RESET, 0)
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/**************************************
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* Config and Parameter
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**************************************/
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#define POWER_ON_VAL1_DEF 0x80015860
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#define SPM_WAKEUP_EVENT_MASK_DEF 0xffffffff
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#define SPM_BUS_PROTECT_MASK_B_DEF 0xffffffff
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#define SPM_BUS_PROTECT2_MASK_B_DEF 0xffffffff
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#define MD32PCM_DMA0_CON_VAL 0x0003820e
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#define MD32PCM_DMA0_START_VAL 0x00008000
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#define MD32PCM_CFGREG_SW_RSTN_RUN 0x1
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#define SPM_DVFS_LEVEL_DEF 0x00000001
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#define SPM_DVS_DFS_LEVEL_DEF 0x00010001
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#define SPM_RESOURCE_ACK_CON0_DEF 0xffffffff
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#define SPM_RESOURCE_ACK_CON1_DEF 0xffffffff
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#define SPM_RESOURCE_ACK_CON2_DEF 0xffffffff
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#define SPM_RESOURCE_ACK_CON3_DEF 0xffffffff
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#define ARMPLL_CLK_SEL_DEF 0x3ff
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#define SPM_SYSCLK_SETTLE 0x60fe
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#define SPM_INIT_DONE_US 20
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#define PCM_WDT_TIMEOUT (30 * 32768)
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#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT)
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/**************************************
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* Definition and Declaration
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**************************************/
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/* SPM_IRQ_MASK */
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DEFINE_BIT(ISRM_TWAM_BF, 2)
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DEFINE_BITFIELD(ISRM_RET_IRQ_AUX_BF, 17, 8)
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#define ISRM_TWAM (1U << 2)
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#define ISRM_RET_IRQ_AUX (0x3ff << 8)
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#define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX)
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#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM)
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/* SPM_IRQ_STA */
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#define ISRS_TWAM (1U << 2)
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#define ISRS_PCM_RETURN (1U << 3)
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#define ISRC_TWAM ISRS_TWAM
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#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN
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#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM)
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/* PCM_PWR_IO_EN */
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#define PCM_PWRIO_EN_R0 (1U << 0)
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#define PCM_PWRIO_EN_R7 (1U << 7)
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#define PCM_RF_SYNC_R0 (1U << 16)
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#define PCM_RF_SYNC_R6 (1U << 22)
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#define PCM_RF_SYNC_R7 (1U << 23)
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/* SPM_SWINT */
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#define PCM_SW_INT_ALL 0x3ff
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struct pwr_ctrl {
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/* for SPM */
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uint32_t pcm_flags;
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/* can override pcm_flags */
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uint32_t pcm_flags_cust;
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/* set bit of pcm_flags, after pcm_flags_cust */
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uint32_t pcm_flags_cust_set;
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/* clr bit of pcm_flags, after pcm_flags_cust */
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uint32_t pcm_flags_cust_clr;
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uint32_t pcm_flags1;
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/* can override pcm_flags1 */
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uint32_t pcm_flags1_cust;
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/* set bit of pcm_flags1, after pcm_flags1_cust */
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uint32_t pcm_flags1_cust_set;
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/* clr bit of pcm_flags1, after pcm_flags1_cust */
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uint32_t pcm_flags1_cust_clr;
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/* @ 1T 32K */
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uint32_t timer_val;
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/* @ 1T 32K, can override timer_val */
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uint32_t timer_val_cust;
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/* stress for dpidle */
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uint32_t timer_val_ramp_en;
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/* stress for suspend */
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uint32_t timer_val_ramp_en_sec;
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uint32_t wake_src;
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/* can override wake_src */
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uint32_t wake_src_cust;
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/* disable wdt in suspend */
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uint8_t wdt_disable;
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/* SPM_AP_STANDBY_CON */
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/* [0] */
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uint8_t reg_wfi_op;
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/* [1] */
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uint8_t reg_wfi_type;
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/* [2] */
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uint8_t reg_mp0_cputop_idle_mask;
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/* [3] */
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uint8_t reg_mp1_cputop_idle_mask;
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/* [4] */
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uint8_t reg_mcusys_idle_mask;
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/* [25] */
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uint8_t reg_md_apsrc_1_sel;
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/* [26] */
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uint8_t reg_md_apsrc_0_sel;
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/* [29] */
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uint8_t reg_conn_apsrc_sel;
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/* SPM_SRC_REQ */
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/* [0] */
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uint8_t reg_spm_apsrc_req;
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/* [1] */
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uint8_t reg_spm_f26m_req;
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/* [3] */
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uint8_t reg_spm_infra_req;
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/* [4] */
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uint8_t reg_spm_vrf18_req;
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/* [7] */
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uint8_t reg_spm_ddr_en_req;
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/* [8] */
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uint8_t reg_spm_dvfs_req;
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/* [9] */
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uint8_t reg_spm_sw_mailbox_req;
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/* [10] */
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uint8_t reg_spm_sspm_mailbox_req;
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/* [11] */
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uint8_t reg_spm_adsp_mailbox_req;
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/* [12] */
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uint8_t reg_spm_scp_mailbox_req;
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/* SPM_SRC_MASK */
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/* [0] */
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uint8_t reg_sspm_srcclkena_0_mask_b;
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/* [1] */
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uint8_t reg_sspm_infra_req_0_mask_b;
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/* [2] */
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uint8_t reg_sspm_apsrc_req_0_mask_b;
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/* [3] */
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uint8_t reg_sspm_vrf18_req_0_mask_b;
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/* [4] */
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uint8_t reg_sspm_ddr_en_0_mask_b;
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/* [5] */
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uint8_t reg_scp_srcclkena_mask_b;
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/* [6] */
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uint8_t reg_scp_infra_req_mask_b;
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/* [7] */
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uint8_t reg_scp_apsrc_req_mask_b;
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/* [8] */
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uint8_t reg_scp_vrf18_req_mask_b;
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/* [9] */
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uint8_t reg_scp_ddr_en_mask_b;
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/* [10] */
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uint8_t reg_audio_dsp_srcclkena_mask_b;
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/* [11] */
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uint8_t reg_audio_dsp_infra_req_mask_b;
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/* [12] */
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uint8_t reg_audio_dsp_apsrc_req_mask_b;
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/* [13] */
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uint8_t reg_audio_dsp_vrf18_req_mask_b;
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/* [14] */
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uint8_t reg_audio_dsp_ddr_en_mask_b;
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/* [15] */
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uint8_t reg_apu_srcclkena_mask_b;
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/* [16] */
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uint8_t reg_apu_infra_req_mask_b;
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/* [17] */
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uint8_t reg_apu_apsrc_req_mask_b;
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/* [18] */
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uint8_t reg_apu_vrf18_req_mask_b;
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/* [19] */
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uint8_t reg_apu_ddr_en_mask_b;
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/* [20] */
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uint8_t reg_cpueb_srcclkena_mask_b;
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/* [21] */
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uint8_t reg_cpueb_infra_req_mask_b;
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/* [22] */
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uint8_t reg_cpueb_apsrc_req_mask_b;
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/* [23] */
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uint8_t reg_cpueb_vrf18_req_mask_b;
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/* [24] */
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uint8_t reg_cpueb_ddr_en_mask_b;
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/* [25] */
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uint8_t reg_bak_psri_srcclkena_mask_b;
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/* [26] */
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uint8_t reg_bak_psri_infra_req_mask_b;
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/* [27] */
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uint8_t reg_bak_psri_apsrc_req_mask_b;
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/* [28] */
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uint8_t reg_bak_psri_vrf18_req_mask_b;
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/* [29] */
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uint8_t reg_bak_psri_ddr_en_mask_b;
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/* SPM_SRC2_MASK */
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/* [0] */
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uint8_t reg_msdc0_srcclkena_mask_b;
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/* [1] */
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uint8_t reg_msdc0_infra_req_mask_b;
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/* [2] */
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uint8_t reg_msdc0_apsrc_req_mask_b;
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/* [3] */
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uint8_t reg_msdc0_vrf18_req_mask_b;
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/* [4] */
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uint8_t reg_msdc0_ddr_en_mask_b;
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/* [5] */
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uint8_t reg_msdc1_srcclkena_mask_b;
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/* [6] */
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uint8_t reg_msdc1_infra_req_mask_b;
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/* [7] */
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uint8_t reg_msdc1_apsrc_req_mask_b;
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/* [8] */
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uint8_t reg_msdc1_vrf18_req_mask_b;
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/* [9] */
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uint8_t reg_msdc1_ddr_en_mask_b;
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/* [10] */
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uint8_t reg_msdc2_srcclkena_mask_b;
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/* [11] */
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uint8_t reg_msdc2_infra_req_mask_b;
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/* [12] */
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uint8_t reg_msdc2_apsrc_req_mask_b;
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/* [13] */
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uint8_t reg_msdc2_vrf18_req_mask_b;
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/* [14] */
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uint8_t reg_msdc2_ddr_en_mask_b;
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/* [15] */
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uint8_t reg_ufs_srcclkena_mask_b;
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/* [16] */
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uint8_t reg_ufs_infra_req_mask_b;
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/* [17] */
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uint8_t reg_ufs_apsrc_req_mask_b;
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/* [18] */
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uint8_t reg_ufs_vrf18_req_mask_b;
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/* [19] */
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uint8_t reg_ufs_ddr_en_mask_b;
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/* [20] */
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uint8_t reg_usb_srcclkena_mask_b;
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/* [21] */
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uint8_t reg_usb_infra_req_mask_b;
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/* [22] */
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uint8_t reg_usb_apsrc_req_mask_b;
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/* [23] */
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uint8_t reg_usb_vrf18_req_mask_b;
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/* [24] */
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uint8_t reg_usb_ddr_en_mask_b;
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/* [25] */
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uint8_t reg_pextp_p0_srcclkena_mask_b;
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/* [26] */
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uint8_t reg_pextp_p0_infra_req_mask_b;
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/* [27] */
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uint8_t reg_pextp_p0_apsrc_req_mask_b;
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/* [28] */
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uint8_t reg_pextp_p0_vrf18_req_mask_b;
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/* [29] */
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uint8_t reg_pextp_p0_ddr_en_mask_b;
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/* SPM_SRC3_MASK */
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/* [0] */
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uint8_t reg_pextp_p1_srcclkena_mask_b;
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/* [1] */
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uint8_t reg_pextp_p1_infra_req_mask_b;
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/* [2] */
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uint8_t reg_pextp_p1_apsrc_req_mask_b;
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/* [3] */
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uint8_t reg_pextp_p1_vrf18_req_mask_b;
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/* [4] */
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uint8_t reg_pextp_p1_ddr_en_mask_b;
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/* [5] */
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uint8_t reg_gce0_infra_req_mask_b;
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/* [6] */
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uint8_t reg_gce0_apsrc_req_mask_b;
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/* [7] */
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uint8_t reg_gce0_vrf18_req_mask_b;
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/* [8] */
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uint8_t reg_gce0_ddr_en_mask_b;
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/* [9] */
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uint8_t reg_gce1_infra_req_mask_b;
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/* [10] */
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uint8_t reg_gce1_apsrc_req_mask_b;
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/* [11] */
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uint8_t reg_gce1_vrf18_req_mask_b;
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/* [12] */
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uint8_t reg_gce1_ddr_en_mask_b;
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/* [13] */
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uint8_t reg_spm_srcclkena_reserved_mask_b;
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/* [14] */
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uint8_t reg_spm_infra_req_reserved_mask_b;
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/* [15] */
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uint8_t reg_spm_apsrc_req_reserved_mask_b;
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/* [16] */
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uint8_t reg_spm_vrf18_req_reserved_mask_b;
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/* [17] */
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uint8_t reg_spm_ddr_en_reserved_mask_b;
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/* [18] */
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uint8_t reg_disp0_apsrc_req_mask_b;
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/* [19] */
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uint8_t reg_disp0_ddr_en_mask_b;
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/* [20] */
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uint8_t reg_disp1_apsrc_req_mask_b;
|
||||
/* [21] */
|
||||
uint8_t reg_disp1_ddr_en_mask_b;
|
||||
/* [22] */
|
||||
uint8_t reg_disp2_apsrc_req_mask_b;
|
||||
/* [23] */
|
||||
uint8_t reg_disp2_ddr_en_mask_b;
|
||||
/* [24] */
|
||||
uint8_t reg_disp3_apsrc_req_mask_b;
|
||||
/* [25] */
|
||||
uint8_t reg_disp3_ddr_en_mask_b;
|
||||
/* [26] */
|
||||
uint8_t reg_infrasys_apsrc_req_mask_b;
|
||||
/* [27] */
|
||||
uint8_t reg_infrasys_ddr_en_mask_b;
|
||||
/* [28] */
|
||||
uint8_t reg_cg_check_srcclkena_mask_b;
|
||||
/* [29] */
|
||||
uint8_t reg_cg_check_apsrc_req_mask_b;
|
||||
/* [30] */
|
||||
uint8_t reg_cg_check_vrf18_req_mask_b;
|
||||
/* [31] */
|
||||
uint8_t reg_cg_check_ddr_en_mask_b;
|
||||
|
||||
/* SPM_SRC4_MASK */
|
||||
/* [8:0] */
|
||||
uint32_t reg_mcusys_merge_apsrc_req_mask_b;
|
||||
/* [17:9] */
|
||||
uint32_t reg_mcusys_merge_ddr_en_mask_b;
|
||||
/* [19:18] */
|
||||
uint8_t reg_dramc_md32_infra_req_mask_b;
|
||||
/* [21:20] */
|
||||
uint8_t reg_dramc_md32_vrf18_req_mask_b;
|
||||
/* [23:22] */
|
||||
uint8_t reg_dramc_md32_ddr_en_mask_b;
|
||||
/* [24] */
|
||||
uint8_t reg_dvfsrc_event_trigger_mask_b;
|
||||
|
||||
/* SPM_WAKEUP_EVENT_MASK2 */
|
||||
/* [3:0] */
|
||||
uint8_t reg_sc_sw2spm_wakeup_mask_b;
|
||||
/* [4] */
|
||||
uint8_t reg_sc_adsp2spm_wakeup_mask_b;
|
||||
/* [8:5] */
|
||||
uint8_t reg_sc_sspm2spm_wakeup_mask_b;
|
||||
/* [9] */
|
||||
uint8_t reg_sc_scp2spm_wakeup_mask_b;
|
||||
/* [10] */
|
||||
uint8_t reg_csyspwrup_ack_mask;
|
||||
/* [11] */
|
||||
uint8_t reg_csyspwrup_req_mask;
|
||||
|
||||
/* SPM_WAKEUP_EVENT_MASK */
|
||||
/* [31:0] */
|
||||
uint32_t reg_wakeup_event_mask;
|
||||
|
||||
/* SPM_WAKEUP_EVENT_EXT_MASK */
|
||||
/* [31:0] */
|
||||
uint32_t reg_ext_wakeup_event_mask;
|
||||
};
|
||||
|
||||
enum {
|
||||
DISP_PWR_STA_MASK = 0x1 << 20,
|
||||
DISP_SRAM_PDN_MASK = 0x1 << 8,
|
||||
DISP_SRAM_ACK_MASK = 0x1 << 12,
|
||||
AUDIO_PWR_STA_MASK = 0x1 << 21,
|
||||
AUDIO_SRAM_PDN_MASK = 0x1 << 8,
|
||||
AUDIO_SRAM_ACK_MASK = 0x1 << 12,
|
||||
};
|
||||
|
||||
struct mtk_spm_regs {
|
||||
u32 poweron_config_set;
|
||||
|
|
@ -496,7 +896,19 @@ struct mtk_spm_regs {
|
|||
u32 spm_twam_window_len;
|
||||
u32 spm_twam_idle_sel;
|
||||
u32 spm_twam_event_clear;
|
||||
u32 rsv_69a0[344];
|
||||
u32 rsv_69a0[24];
|
||||
u32 md32pcm_cfgreg_sw_rstn;
|
||||
u32 rsv_a04[127];
|
||||
u32 md32pcm_dma0_src;
|
||||
u32 md32pcm_dma0_dst;
|
||||
u32 md32pcm_dma0_wppt;
|
||||
u32 md32pcm_dma0_wpto;
|
||||
u32 md32pcm_dma0_count;
|
||||
u32 md32pcm_dma0_con;
|
||||
u32 md32pcm_dma0_start;
|
||||
u32 rsv_c1c[2];
|
||||
u32 md32pcm_dma0_rlct;
|
||||
u32 rsv_c28[182];
|
||||
u32 pmsr_last_dat;
|
||||
u32 pmsr_last_cnt;
|
||||
u32 pmsr_last_ack;
|
||||
|
|
@ -540,6 +952,20 @@ check_member(mtk_spm_regs, ulposc_con, 0x644);
|
|||
|
||||
static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;
|
||||
|
||||
struct pcm_desc {
|
||||
u32 pmem_words;
|
||||
u32 total_words;
|
||||
u32 pmem_start;
|
||||
u32 dmem_start;
|
||||
};
|
||||
|
||||
struct dyna_load_pcm {
|
||||
u8 *buf; /* binary array */
|
||||
struct pcm_desc desc;
|
||||
};
|
||||
|
||||
int spm_init(void);
|
||||
|
||||
static const struct power_domain_data disp[] = {
|
||||
{
|
||||
.pwr_con = &mtk_spm->vppsys0_pwr_con,
|
||||
|
|
@ -568,18 +994,11 @@ static const struct power_domain_data disp[] = {
|
|||
};
|
||||
|
||||
static const struct power_domain_data audio[] = {
|
||||
{
|
||||
.pwr_con = &mtk_spm->adsp_pwr_con,
|
||||
.pwr_sta_mask = 0x1 << 10,
|
||||
.sram_pdn_mask = 0x1 << 8,
|
||||
.sram_ack_mask = 0x1 << 12,
|
||||
.caps = SCPD_SRAM_ISO,
|
||||
},
|
||||
{
|
||||
.pwr_con = &mtk_spm->audio_pwr_con,
|
||||
.pwr_sta_mask = 0x1 << 8,
|
||||
.sram_pdn_mask = 0x1 << 8,
|
||||
.sram_ack_mask = 0x1 << 12,
|
||||
.pwr_sta_mask = AUDIO_PWR_STA_MASK,
|
||||
.sram_pdn_mask = AUDIO_SRAM_PDN_MASK,
|
||||
.sram_ack_mask = AUDIO_SRAM_ACK_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,714 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <assert.h>
|
||||
#include <console/console.h>
|
||||
#include <delay.h>
|
||||
#include <device/mmio.h>
|
||||
#include <soc/mcu_common.h>
|
||||
#include <soc/spm.h>
|
||||
#include <soc/spm_common.h>
|
||||
#include <soc/symbols.h>
|
||||
#include <string.h>
|
||||
#include <timer.h>
|
||||
|
||||
#define SPM_SYSTEM_BASE_OFFSET 0x40000000
|
||||
|
||||
static const struct pwr_ctrl spm_init_ctrl = {
|
||||
.pcm_flags = SPM_FLAG_DISABLE_VCORE_DVS | SPM_FLAG_DISABLE_VCORE_DFS |
|
||||
SPM_FLAG_RUN_COMMON_SCENARIO,
|
||||
|
||||
/* SPM_AP_STANDBY_CON */
|
||||
/* [0] */
|
||||
.reg_wfi_op = 0,
|
||||
/* [1] */
|
||||
.reg_wfi_type = 0,
|
||||
/* [2] */
|
||||
.reg_mp0_cputop_idle_mask = 0,
|
||||
/* [3] */
|
||||
.reg_mp1_cputop_idle_mask = 0,
|
||||
/* [4] */
|
||||
.reg_mcusys_idle_mask = 0,
|
||||
/* [25] */
|
||||
.reg_md_apsrc_1_sel = 0,
|
||||
/* [26] */
|
||||
.reg_md_apsrc_0_sel = 0,
|
||||
/* [29] */
|
||||
.reg_conn_apsrc_sel = 0,
|
||||
|
||||
/* SPM_SRC_REQ */
|
||||
/* [0] */
|
||||
.reg_spm_apsrc_req = 0,
|
||||
/* [1] */
|
||||
.reg_spm_f26m_req = 0,
|
||||
/* [3] */
|
||||
.reg_spm_infra_req = 0,
|
||||
/* [4] */
|
||||
.reg_spm_vrf18_req = 0,
|
||||
/* [7] FIXME: default disable HW Auto S1*/
|
||||
.reg_spm_ddr_en_req = 1,
|
||||
/* [8] */
|
||||
.reg_spm_dvfs_req = 0,
|
||||
/* [9] */
|
||||
.reg_spm_sw_mailbox_req = 0,
|
||||
/* [10] */
|
||||
.reg_spm_sspm_mailbox_req = 0,
|
||||
/* [11] */
|
||||
.reg_spm_adsp_mailbox_req = 0,
|
||||
/* [12] */
|
||||
.reg_spm_scp_mailbox_req = 0,
|
||||
|
||||
/* SPM_SRC_MASK */
|
||||
/* [0] */
|
||||
.reg_sspm_srcclkena_0_mask_b = 1,
|
||||
/* [1] */
|
||||
.reg_sspm_infra_req_0_mask_b = 1,
|
||||
/* [2] */
|
||||
.reg_sspm_apsrc_req_0_mask_b = 1,
|
||||
/* [3] */
|
||||
.reg_sspm_vrf18_req_0_mask_b = 1,
|
||||
/* [4] */
|
||||
.reg_sspm_ddr_en_0_mask_b = 1,
|
||||
/* [5] */
|
||||
.reg_scp_srcclkena_mask_b = 1,
|
||||
/* [6] */
|
||||
.reg_scp_infra_req_mask_b = 1,
|
||||
/* [7] */
|
||||
.reg_scp_apsrc_req_mask_b = 1,
|
||||
/* [8] */
|
||||
.reg_scp_vrf18_req_mask_b = 1,
|
||||
/* [9] */
|
||||
.reg_scp_ddr_en_mask_b = 1,
|
||||
/* [10] */
|
||||
.reg_audio_dsp_srcclkena_mask_b = 1,
|
||||
/* [11] */
|
||||
.reg_audio_dsp_infra_req_mask_b = 1,
|
||||
/* [12] */
|
||||
.reg_audio_dsp_apsrc_req_mask_b = 1,
|
||||
/* [13] */
|
||||
.reg_audio_dsp_vrf18_req_mask_b = 1,
|
||||
/* [14] */
|
||||
.reg_audio_dsp_ddr_en_mask_b = 1,
|
||||
/* [15] */
|
||||
.reg_apu_srcclkena_mask_b = 1,
|
||||
/* [16] */
|
||||
.reg_apu_infra_req_mask_b = 1,
|
||||
/* [17] */
|
||||
.reg_apu_apsrc_req_mask_b = 1,
|
||||
/* [18] */
|
||||
.reg_apu_vrf18_req_mask_b = 1,
|
||||
/* [19] */
|
||||
.reg_apu_ddr_en_mask_b = 1,
|
||||
/* [20] */
|
||||
.reg_cpueb_srcclkena_mask_b = 1,
|
||||
/* [21] */
|
||||
.reg_cpueb_infra_req_mask_b = 1,
|
||||
/* [22] */
|
||||
.reg_cpueb_apsrc_req_mask_b = 1,
|
||||
/* [23] */
|
||||
.reg_cpueb_vrf18_req_mask_b = 1,
|
||||
/* [24] */
|
||||
.reg_cpueb_ddr_en_mask_b = 1,
|
||||
/* [25] */
|
||||
.reg_bak_psri_srcclkena_mask_b = 0,
|
||||
/* [26] */
|
||||
.reg_bak_psri_infra_req_mask_b = 0,
|
||||
/* [27] */
|
||||
.reg_bak_psri_apsrc_req_mask_b = 0,
|
||||
/* [28] */
|
||||
.reg_bak_psri_vrf18_req_mask_b = 0,
|
||||
/* [29] */
|
||||
.reg_bak_psri_ddr_en_mask_b = 0,
|
||||
|
||||
/* SPM_SRC2_MASK */
|
||||
/* [0] */
|
||||
.reg_msdc0_srcclkena_mask_b = 1,
|
||||
/* [1] */
|
||||
.reg_msdc0_infra_req_mask_b = 1,
|
||||
/* [2] */
|
||||
.reg_msdc0_apsrc_req_mask_b = 1,
|
||||
/* [3] */
|
||||
.reg_msdc0_vrf18_req_mask_b = 1,
|
||||
/* [4] */
|
||||
.reg_msdc0_ddr_en_mask_b = 1,
|
||||
/* [5] */
|
||||
.reg_msdc1_srcclkena_mask_b = 1,
|
||||
/* [6] */
|
||||
.reg_msdc1_infra_req_mask_b = 1,
|
||||
/* [7] */
|
||||
.reg_msdc1_apsrc_req_mask_b = 1,
|
||||
/* [8] */
|
||||
.reg_msdc1_vrf18_req_mask_b = 1,
|
||||
/* [9] */
|
||||
.reg_msdc1_ddr_en_mask_b = 1,
|
||||
/* [10] */
|
||||
.reg_msdc2_srcclkena_mask_b = 1,
|
||||
/* [11] */
|
||||
.reg_msdc2_infra_req_mask_b = 1,
|
||||
/* [12] */
|
||||
.reg_msdc2_apsrc_req_mask_b = 1,
|
||||
/* [13] */
|
||||
.reg_msdc2_vrf18_req_mask_b = 1,
|
||||
/* [14] */
|
||||
.reg_msdc2_ddr_en_mask_b = 1,
|
||||
/* [15] */
|
||||
.reg_ufs_srcclkena_mask_b = 1,
|
||||
/* [16] */
|
||||
.reg_ufs_infra_req_mask_b = 1,
|
||||
/* [17] */
|
||||
.reg_ufs_apsrc_req_mask_b = 1,
|
||||
/* [18] */
|
||||
.reg_ufs_vrf18_req_mask_b = 1,
|
||||
/* [19] */
|
||||
.reg_ufs_ddr_en_mask_b = 1,
|
||||
/* [20] */
|
||||
.reg_usb_srcclkena_mask_b = 1,
|
||||
/* [21] */
|
||||
.reg_usb_infra_req_mask_b = 1,
|
||||
/* [22] */
|
||||
.reg_usb_apsrc_req_mask_b = 1,
|
||||
/* [23] */
|
||||
.reg_usb_vrf18_req_mask_b = 1,
|
||||
/* [24] */
|
||||
.reg_usb_ddr_en_mask_b = 1,
|
||||
/* [25] */
|
||||
.reg_pextp_p0_srcclkena_mask_b = 1,
|
||||
/* [26] */
|
||||
.reg_pextp_p0_infra_req_mask_b = 1,
|
||||
/* [27] */
|
||||
.reg_pextp_p0_apsrc_req_mask_b = 1,
|
||||
/* [28] */
|
||||
.reg_pextp_p0_vrf18_req_mask_b = 1,
|
||||
/* [29] */
|
||||
.reg_pextp_p0_ddr_en_mask_b = 1,
|
||||
|
||||
/* SPM_SRC3_MASK */
|
||||
/* [0] */
|
||||
.reg_pextp_p1_srcclkena_mask_b = 1,
|
||||
/* [1] */
|
||||
.reg_pextp_p1_infra_req_mask_b = 1,
|
||||
/* [2] */
|
||||
.reg_pextp_p1_apsrc_req_mask_b = 1,
|
||||
/* [3] */
|
||||
.reg_pextp_p1_vrf18_req_mask_b = 1,
|
||||
/* [4] */
|
||||
.reg_pextp_p1_ddr_en_mask_b = 1,
|
||||
/* [5] */
|
||||
.reg_gce0_infra_req_mask_b = 1,
|
||||
/* [6] */
|
||||
.reg_gce0_apsrc_req_mask_b = 1,
|
||||
/* [7] */
|
||||
.reg_gce0_vrf18_req_mask_b = 1,
|
||||
/* [8] */
|
||||
.reg_gce0_ddr_en_mask_b = 1,
|
||||
/* [9] */
|
||||
.reg_gce1_infra_req_mask_b = 1,
|
||||
/* [10] */
|
||||
.reg_gce1_apsrc_req_mask_b = 1,
|
||||
/* [11] */
|
||||
.reg_gce1_vrf18_req_mask_b = 1,
|
||||
/* [12] */
|
||||
.reg_gce1_ddr_en_mask_b = 1,
|
||||
/* [13] */
|
||||
.reg_spm_srcclkena_reserved_mask_b = 1,
|
||||
/* [14] */
|
||||
.reg_spm_infra_req_reserved_mask_b = 1,
|
||||
/* [15] */
|
||||
.reg_spm_apsrc_req_reserved_mask_b = 1,
|
||||
/* [16] */
|
||||
.reg_spm_vrf18_req_reserved_mask_b = 1,
|
||||
/* [17] */
|
||||
.reg_spm_ddr_en_reserved_mask_b = 1,
|
||||
/* [18] */
|
||||
.reg_disp0_apsrc_req_mask_b = 1,
|
||||
/* [19] */
|
||||
.reg_disp0_ddr_en_mask_b = 1,
|
||||
/* [20] */
|
||||
.reg_disp1_apsrc_req_mask_b = 1,
|
||||
/* [21] */
|
||||
.reg_disp1_ddr_en_mask_b = 1,
|
||||
/* [22] */
|
||||
.reg_disp2_apsrc_req_mask_b = 1,
|
||||
/* [23] */
|
||||
.reg_disp2_ddr_en_mask_b = 1,
|
||||
/* [24] */
|
||||
.reg_disp3_apsrc_req_mask_b = 1,
|
||||
/* [25] */
|
||||
.reg_disp3_ddr_en_mask_b = 1,
|
||||
/* [26] */
|
||||
.reg_infrasys_apsrc_req_mask_b = 0,
|
||||
/* [27] */
|
||||
.reg_infrasys_ddr_en_mask_b = 1,
|
||||
|
||||
/* [28] */
|
||||
.reg_cg_check_srcclkena_mask_b = 1,
|
||||
/* [29] */
|
||||
.reg_cg_check_apsrc_req_mask_b = 1,
|
||||
/* [30] */
|
||||
.reg_cg_check_vrf18_req_mask_b = 1,
|
||||
/* [31] */
|
||||
.reg_cg_check_ddr_en_mask_b = 1,
|
||||
|
||||
/* SPM_SRC4_MASK */
|
||||
/* [8:0] */
|
||||
.reg_mcusys_merge_apsrc_req_mask_b = 0x17,
|
||||
/* [17:9] */
|
||||
.reg_mcusys_merge_ddr_en_mask_b = 0x17,
|
||||
/* [19:18] */
|
||||
.reg_dramc_md32_infra_req_mask_b = 0,
|
||||
/* [21:20] */
|
||||
.reg_dramc_md32_vrf18_req_mask_b = 0,
|
||||
/* [23:22] */
|
||||
.reg_dramc_md32_ddr_en_mask_b = 0,
|
||||
/* [24] */
|
||||
.reg_dvfsrc_event_trigger_mask_b = 1,
|
||||
|
||||
/* SPM_WAKEUP_EVENT_MASK2 */
|
||||
/* [3:0] */
|
||||
.reg_sc_sw2spm_wakeup_mask_b = 0,
|
||||
/* [4] */
|
||||
.reg_sc_adsp2spm_wakeup_mask_b = 0,
|
||||
/* [8:5] */
|
||||
.reg_sc_sspm2spm_wakeup_mask_b = 0,
|
||||
/* [9] */
|
||||
.reg_sc_scp2spm_wakeup_mask_b = 0,
|
||||
/* [10] */
|
||||
.reg_csyspwrup_ack_mask = 0,
|
||||
/* [11] */
|
||||
.reg_csyspwrup_req_mask = 1,
|
||||
|
||||
/* SPM_WAKEUP_EVENT_MASK */
|
||||
/* [31:0] */
|
||||
.reg_wakeup_event_mask = 0xC1382213,
|
||||
|
||||
/* SPM_WAKEUP_EVENT_EXT_MASK */
|
||||
/* [31:0] */
|
||||
.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
|
||||
};
|
||||
|
||||
static void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
|
||||
{
|
||||
/* Auto-gen Start */
|
||||
|
||||
/* SPM_AP_STANDBY_CON */
|
||||
write32(&mtk_spm->spm_ap_standby_con,
|
||||
((pwrctrl->reg_wfi_op & 0x1) << 0) |
|
||||
((pwrctrl->reg_wfi_type & 0x1) << 1) |
|
||||
((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
|
||||
((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
|
||||
((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
|
||||
((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
|
||||
((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
|
||||
((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
|
||||
|
||||
/* SPM_SRC_REQ */
|
||||
write32(&mtk_spm->spm_src_req,
|
||||
((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
|
||||
((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
|
||||
((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
|
||||
((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
|
||||
((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) |
|
||||
((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
|
||||
((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
|
||||
((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
|
||||
((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
|
||||
((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
|
||||
|
||||
/* SPM_SRC_MASK */
|
||||
write32(&mtk_spm->spm_src_mask,
|
||||
((pwrctrl->reg_sspm_srcclkena_0_mask_b & 0x1) << 0) |
|
||||
((pwrctrl->reg_sspm_infra_req_0_mask_b & 0x1) << 1) |
|
||||
((pwrctrl->reg_sspm_apsrc_req_0_mask_b & 0x1) << 2) |
|
||||
((pwrctrl->reg_sspm_vrf18_req_0_mask_b & 0x1) << 3) |
|
||||
((pwrctrl->reg_sspm_ddr_en_0_mask_b & 0x1) << 4) |
|
||||
((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 5) |
|
||||
((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 6) |
|
||||
((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 7) |
|
||||
((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 8) |
|
||||
((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 9) |
|
||||
((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 10) |
|
||||
((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 11) |
|
||||
((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 12) |
|
||||
((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 13) |
|
||||
((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 14) |
|
||||
((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 15) |
|
||||
((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 16) |
|
||||
((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 17) |
|
||||
((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 18) |
|
||||
((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 19) |
|
||||
((pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 20) |
|
||||
((pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 21) |
|
||||
((pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 22) |
|
||||
((pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 23) |
|
||||
((pwrctrl->reg_cpueb_ddr_en_mask_b & 0x1) << 24) |
|
||||
((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 25) |
|
||||
((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 26) |
|
||||
((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 27) |
|
||||
((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 28) |
|
||||
((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 29));
|
||||
|
||||
/* SPM_SRC2_MASK */
|
||||
write32(&mtk_spm->spm_src2_mask,
|
||||
((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 0) |
|
||||
((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 1) |
|
||||
((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 2) |
|
||||
((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 3) |
|
||||
((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 4) |
|
||||
((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 5) |
|
||||
((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 6) |
|
||||
((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 7) |
|
||||
((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 8) |
|
||||
((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 9) |
|
||||
((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 10) |
|
||||
((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 11) |
|
||||
((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 12) |
|
||||
((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 13) |
|
||||
((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 14) |
|
||||
((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 15) |
|
||||
((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 16) |
|
||||
((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 17) |
|
||||
((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 18) |
|
||||
((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 19) |
|
||||
((pwrctrl->reg_usb_srcclkena_mask_b & 0x1) << 20) |
|
||||
((pwrctrl->reg_usb_infra_req_mask_b & 0x1) << 21) |
|
||||
((pwrctrl->reg_usb_apsrc_req_mask_b & 0x1) << 22) |
|
||||
((pwrctrl->reg_usb_vrf18_req_mask_b & 0x1) << 23) |
|
||||
((pwrctrl->reg_usb_ddr_en_mask_b & 0x1) << 24) |
|
||||
((pwrctrl->reg_pextp_p0_srcclkena_mask_b & 0x1) << 25) |
|
||||
((pwrctrl->reg_pextp_p0_infra_req_mask_b & 0x1) << 26) |
|
||||
((pwrctrl->reg_pextp_p0_apsrc_req_mask_b & 0x1) << 27) |
|
||||
((pwrctrl->reg_pextp_p0_vrf18_req_mask_b & 0x1) << 28) |
|
||||
((pwrctrl->reg_pextp_p0_ddr_en_mask_b & 0x1) << 29));
|
||||
|
||||
/* SPM_SRC3_MASK */
|
||||
write32(&mtk_spm->spm_src3_mask,
|
||||
((pwrctrl->reg_pextp_p1_srcclkena_mask_b & 0x1) << 0) |
|
||||
((pwrctrl->reg_pextp_p1_infra_req_mask_b & 0x1) << 1) |
|
||||
((pwrctrl->reg_pextp_p1_apsrc_req_mask_b & 0x1) << 2) |
|
||||
((pwrctrl->reg_pextp_p1_vrf18_req_mask_b & 0x1) << 3) |
|
||||
((pwrctrl->reg_pextp_p1_ddr_en_mask_b & 0x1) << 4) |
|
||||
((pwrctrl->reg_gce0_infra_req_mask_b & 0x1) << 5) |
|
||||
((pwrctrl->reg_gce0_apsrc_req_mask_b & 0x1) << 6) |
|
||||
((pwrctrl->reg_gce0_vrf18_req_mask_b & 0x1) << 7) |
|
||||
((pwrctrl->reg_gce0_ddr_en_mask_b & 0x1) << 8) |
|
||||
((pwrctrl->reg_gce1_infra_req_mask_b & 0x1) << 9) |
|
||||
((pwrctrl->reg_gce1_apsrc_req_mask_b & 0x1) << 10) |
|
||||
((pwrctrl->reg_gce1_vrf18_req_mask_b & 0x1) << 11) |
|
||||
((pwrctrl->reg_gce1_ddr_en_mask_b & 0x1) << 12) |
|
||||
((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 13) |
|
||||
((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 14) |
|
||||
((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 15) |
|
||||
((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 16) |
|
||||
((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 17) |
|
||||
((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 18) |
|
||||
((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 19) |
|
||||
((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 20) |
|
||||
((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 21) |
|
||||
((pwrctrl->reg_disp2_apsrc_req_mask_b & 0x1) << 22) |
|
||||
((pwrctrl->reg_disp2_ddr_en_mask_b & 0x1) << 23) |
|
||||
((pwrctrl->reg_disp3_apsrc_req_mask_b & 0x1) << 24) |
|
||||
((pwrctrl->reg_disp3_ddr_en_mask_b & 0x1) << 25) |
|
||||
((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 26) |
|
||||
((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 27));
|
||||
|
||||
/* SPM_SRC4_MASK */
|
||||
write32(&mtk_spm->spm_src4_mask, 0x1fc0000);
|
||||
|
||||
/* SPM_WAKEUP_EVENT_MASK */
|
||||
write32(&mtk_spm->spm_wakeup_event_mask,
|
||||
((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
|
||||
|
||||
/* SPM_WAKEUP_EVENT_EXT_MASK */
|
||||
write32(&mtk_spm->spm_wakeup_event_ext_mask,
|
||||
((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
|
||||
|
||||
/* Auto-gen End */
|
||||
}
|
||||
|
||||
static void spm_register_init(void)
|
||||
{
|
||||
/* Enable register control */
|
||||
write32(&mtk_spm->poweron_config_set,
|
||||
SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
|
||||
|
||||
/* Init power control register */
|
||||
write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF);
|
||||
write32(&mtk_spm->pcm_pwr_io_en, 0);
|
||||
|
||||
/* Reset PCM */
|
||||
write32(&mtk_spm->pcm_con0,
|
||||
SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB);
|
||||
write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
|
||||
write32(&mtk_spm->pcm_con1,
|
||||
SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB |
|
||||
REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB |
|
||||
REG_MD32_APB_INTERNAL_EN_LSB);
|
||||
|
||||
/* Initial SPM CLK control register */
|
||||
SET32_BITFIELDS(&mtk_spm->spm_clk_con,
|
||||
REG_SYSCLK1_SRC_MD2_SRCCLKENA, 1);
|
||||
|
||||
/* Clean wakeup event raw status */
|
||||
write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF);
|
||||
|
||||
/* Clean ISR status */
|
||||
write32(&mtk_spm->spm_irq_mask, ISRM_ALL);
|
||||
write32(&mtk_spm->spm_irq_sta, ISRC_ALL);
|
||||
write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL);
|
||||
|
||||
/* Init r7 with POWER_ON_VAL1 */
|
||||
write32(&mtk_spm->pcm_reg_data_ini,
|
||||
read32(&mtk_spm->spm_power_on_val1));
|
||||
write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
|
||||
write32(&mtk_spm->pcm_pwr_io_en, 0);
|
||||
|
||||
/* Configure ARMPLL Control Mode for MCDI */
|
||||
write32(&mtk_spm->armpll_clk_sel, ARMPLL_CLK_SEL_DEF);
|
||||
|
||||
/* Init for SPM Resource ACK */
|
||||
write32(&mtk_spm->spm_resource_ack_con0, SPM_RESOURCE_ACK_CON0_DEF);
|
||||
write32(&mtk_spm->spm_resource_ack_con1, SPM_RESOURCE_ACK_CON1_DEF);
|
||||
write32(&mtk_spm->spm_resource_ack_con2, SPM_RESOURCE_ACK_CON2_DEF);
|
||||
write32(&mtk_spm->spm_resource_ack_con3, SPM_RESOURCE_ACK_CON3_DEF);
|
||||
|
||||
/* Init VCORE DVFS Status */
|
||||
SET32_BITFIELDS(&mtk_spm->spm_dvfs_misc,
|
||||
SPM_DVFS_FORCE_ENABLE_LSB, 0,
|
||||
SPM_DVFSRC_ENABLE_LSB, 1);
|
||||
write32(&mtk_spm->spm_dvfs_level, SPM_DVFS_LEVEL_DEF);
|
||||
write32(&mtk_spm->spm_dvs_dfs_level, SPM_DVS_DFS_LEVEL_DEF);
|
||||
|
||||
}
|
||||
|
||||
static void spm_set_sysclk_settle(void)
|
||||
{
|
||||
write32(&mtk_spm->spm_clk_settle, SPM_SYSCLK_SETTLE);
|
||||
}
|
||||
|
||||
static void spm_code_swapping(void)
|
||||
{
|
||||
u32 mask;
|
||||
|
||||
mask = read32(&mtk_spm->spm_wakeup_event_mask);
|
||||
write32(&mtk_spm->spm_wakeup_event_mask,
|
||||
mask & ~SPM_WAKEUP_EVENT_MASK_BIT0);
|
||||
write32(&mtk_spm->spm_cpu_wakeup_event, 1);
|
||||
write32(&mtk_spm->spm_cpu_wakeup_event, 0);
|
||||
write32(&mtk_spm->spm_wakeup_event_mask, mask);
|
||||
}
|
||||
|
||||
static void spm_reset_and_init_pcm(void)
|
||||
{
|
||||
bool first_load_fw = true;
|
||||
|
||||
/* Check the SPM FW is run or not */
|
||||
if (read32(&mtk_spm->md32pcm_cfgreg_sw_rstn) &
|
||||
MD32PCM_CFGREG_SW_RSTN_RUN)
|
||||
first_load_fw = false;
|
||||
|
||||
if (!first_load_fw) {
|
||||
spm_code_swapping();
|
||||
/* Backup PCM r0 -> SPM_POWER_ON_VAL0 before reset PCM */
|
||||
write32(&mtk_spm->spm_power_on_val0,
|
||||
read32(&mtk_spm->pcm_reg0_data));
|
||||
}
|
||||
|
||||
/* Disable r0 and r7 to control power */
|
||||
write32(&mtk_spm->pcm_pwr_io_en, 0);
|
||||
|
||||
/* Disable pcm timer after leaving FW */
|
||||
clrsetbits32(&mtk_spm->pcm_con1,
|
||||
RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
|
||||
|
||||
/* Reset PCM */
|
||||
write32(&mtk_spm->pcm_con0,
|
||||
SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB);
|
||||
write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
|
||||
|
||||
/* Init PCM_CON1 (disable PCM timer but keep PCM WDT setting) */
|
||||
clrsetbits32(&mtk_spm->pcm_con1, ~RG_PCM_WDT_WAKE_LSB,
|
||||
SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB |
|
||||
REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB |
|
||||
REG_MD32_APB_INTERNAL_EN_LSB);
|
||||
}
|
||||
|
||||
static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm)
|
||||
{
|
||||
uintptr_t ptr;
|
||||
u32 dmem_words;
|
||||
u32 pmem_words;
|
||||
u32 total_words;
|
||||
u32 pmem_start;
|
||||
u32 dmem_start;
|
||||
|
||||
ptr = (uintptr_t)pcm->buf + SPM_SYSTEM_BASE_OFFSET;
|
||||
pmem_words = pcm->desc.pmem_words;
|
||||
total_words = pcm->desc.total_words;
|
||||
dmem_words = total_words - pmem_words;
|
||||
pmem_start = pcm->desc.pmem_start;
|
||||
dmem_start = pcm->desc.dmem_start;
|
||||
|
||||
printk(BIOS_DEBUG, "%s: ptr = %#lx, pmem/dmem words = %#x/%#x\n",
|
||||
__func__, (long)ptr, pmem_words, dmem_words);
|
||||
|
||||
/* DMA needs 16-byte aligned source data. */
|
||||
assert(ptr % 16 == 0);
|
||||
|
||||
write32(&mtk_spm->md32pcm_dma0_src, ptr);
|
||||
write32(&mtk_spm->md32pcm_dma0_dst, pmem_start);
|
||||
write32(&mtk_spm->md32pcm_dma0_wppt, pmem_words);
|
||||
write32(&mtk_spm->md32pcm_dma0_wpto, dmem_start);
|
||||
write32(&mtk_spm->md32pcm_dma0_count, total_words);
|
||||
write32(&mtk_spm->md32pcm_dma0_con, MD32PCM_DMA0_CON_VAL);
|
||||
write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL);
|
||||
|
||||
setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
|
||||
}
|
||||
|
||||
static void spm_init_pcm_register(void)
|
||||
{
|
||||
/* Init r0 with POWER_ON_VAL0 */
|
||||
write32(&mtk_spm->pcm_reg_data_ini,
|
||||
read32(&mtk_spm->spm_power_on_val0));
|
||||
write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0);
|
||||
write32(&mtk_spm->pcm_pwr_io_en, 0);
|
||||
|
||||
/* Init r7 with POWER_ON_VAL1 */
|
||||
write32(&mtk_spm->pcm_reg_data_ini,
|
||||
read32(&mtk_spm->spm_power_on_val1));
|
||||
write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
|
||||
write32(&mtk_spm->pcm_pwr_io_en, 0);
|
||||
}
|
||||
|
||||
static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
|
||||
{
|
||||
u32 val, mask;
|
||||
|
||||
/* Toggle event counter clear */
|
||||
setbits32(&mtk_spm->pcm_con1,
|
||||
SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB);
|
||||
|
||||
/* Toggle for reset SYS TIMER start point */
|
||||
SET32_BITFIELDS(&mtk_spm->sys_timer_con,
|
||||
SYS_TIMER_START_EN_LSB, 1);
|
||||
|
||||
if (pwrctrl->timer_val_cust == 0)
|
||||
val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX;
|
||||
else
|
||||
val = pwrctrl->timer_val_cust;
|
||||
|
||||
write32(&mtk_spm->pcm_timer_val, val);
|
||||
|
||||
/* Disable pcm timer */
|
||||
clrsetbits32(&mtk_spm->pcm_con1,
|
||||
RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
|
||||
|
||||
/* Unmask AP wakeup source */
|
||||
if (pwrctrl->wake_src_cust == 0)
|
||||
mask = pwrctrl->wake_src;
|
||||
else
|
||||
mask = pwrctrl->wake_src_cust;
|
||||
|
||||
write32(&mtk_spm->spm_wakeup_event_mask, ~mask);
|
||||
|
||||
/* Unmask SPM ISR */
|
||||
SET32_BITFIELDS(&mtk_spm->spm_irq_mask,
|
||||
ISRM_TWAM_BF, 1,
|
||||
ISRM_RET_IRQ_AUX_BF, 0x3ff);
|
||||
|
||||
/* Toggle event counter clear */
|
||||
clrsetbits32(&mtk_spm->pcm_con1,
|
||||
SPM_EVENT_COUNTER_CLR_LSB, SPM_REGWR_CFG_KEY);
|
||||
|
||||
/* Toggle for reset SYS TIMER start point */
|
||||
SET32_BITFIELDS(&mtk_spm->sys_timer_con,
|
||||
SYS_TIMER_START_EN_LSB, 0);
|
||||
}
|
||||
|
||||
static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl)
|
||||
{
|
||||
u32 pcm_flags = pwrctrl->pcm_flags, pcm_flags1 = pwrctrl->pcm_flags1;
|
||||
|
||||
/* Set PCM flags and data */
|
||||
if (pwrctrl->pcm_flags_cust_clr != 0)
|
||||
pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
|
||||
if (pwrctrl->pcm_flags_cust_set != 0)
|
||||
pcm_flags |= pwrctrl->pcm_flags_cust_set;
|
||||
if (pwrctrl->pcm_flags1_cust_clr != 0)
|
||||
pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
|
||||
if (pwrctrl->pcm_flags1_cust_set != 0)
|
||||
pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
|
||||
|
||||
write32(&mtk_spm->spm_sw_flag_0, pcm_flags);
|
||||
write32(&mtk_spm->spm_sw_flag_1, pcm_flags1);
|
||||
write32(&mtk_spm->spm_sw_rsv_7, pcm_flags);
|
||||
write32(&mtk_spm->spm_sw_rsv_8, pcm_flags1);
|
||||
}
|
||||
|
||||
static void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl)
|
||||
{
|
||||
/* Waiting for loading SPMFW done*/
|
||||
while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0)
|
||||
;
|
||||
|
||||
/* Init register to match PCM expectation */
|
||||
write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF);
|
||||
write32(&mtk_spm->spm_bus_protect2_mask_b,
|
||||
SPM_BUS_PROTECT2_MASK_B_DEF);
|
||||
write32(&mtk_spm->pcm_reg_data_ini, 0);
|
||||
|
||||
spm_set_pcm_flags(pwrctrl);
|
||||
|
||||
/* Kick PCM to run (only toggle PCM_KICK) */
|
||||
setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
|
||||
|
||||
/* Reset md32pcm */
|
||||
SET32_BITFIELDS(&mtk_spm->md32pcm_cfgreg_sw_rstn,
|
||||
MD32PCM_CFGREG_SW_RSTN_RESET, 1);
|
||||
|
||||
/* Waiting for SPM init done */
|
||||
udelay(SPM_INIT_DONE_US);
|
||||
}
|
||||
|
||||
static void reset_spm(struct mtk_mcu *mcu)
|
||||
{
|
||||
struct dyna_load_pcm *pcm = (struct dyna_load_pcm *)mcu->priv;
|
||||
|
||||
spm_parse_firmware(mcu);
|
||||
spm_reset_and_init_pcm();
|
||||
spm_kick_im_to_fetch(pcm);
|
||||
spm_init_pcm_register();
|
||||
spm_set_wakeup_event(&spm_init_ctrl);
|
||||
spm_kick_pcm_to_run(&spm_init_ctrl);
|
||||
}
|
||||
|
||||
static struct mtk_mcu spm = {
|
||||
.firmware_name = CONFIG_SPM_FIRMWARE,
|
||||
.reset = reset_spm,
|
||||
};
|
||||
|
||||
int spm_init(void)
|
||||
{
|
||||
struct dyna_load_pcm pcm;
|
||||
struct stopwatch sw;
|
||||
|
||||
stopwatch_init(&sw);
|
||||
|
||||
spm_register_init();
|
||||
spm_set_power_control(&spm_init_ctrl);
|
||||
spm_set_sysclk_settle();
|
||||
|
||||
spm.load_buffer = _dram_dma;
|
||||
spm.buffer_size = REGION_SIZE(dram_dma);
|
||||
spm.priv = (void *)&pcm;
|
||||
|
||||
if (mtk_init_mcu(&spm)) {
|
||||
printk(BIOS_ERR, "SPM: %s: failed in mtk_init_mcu\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "SPM: %s done in %ld msecs, spm pc = %#x\n",
|
||||
__func__, stopwatch_duration_msecs(&sw),
|
||||
read32(&mtk_spm->md32pcm_pc));
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue