cpu/intel/haswell: Move chip_ops to cpu cluster

The cpu cluster is always present and it's the proper device to contain
the settings that need to be applied to all cpus. This makes it possible
to remove the fake lapic from devicetrees.

Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59314
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

src/cpu/intel/haswell/acpi.c

@@ -164,28 +164,22 @@ static void generate_T_state_entries(int core, int cores_per_package)
 			ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
 }
 
-static bool is_s0ix_enabled(void)
+static bool is_s0ix_enabled(const struct device *dev)
 {
 	if (!haswell_is_ult())
 		return false;
 
-	const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+	const struct cpu_intel_haswell_config *conf = dev->chip_info;
-
-	if (!lapic || !lapic->chip_info)
-		return false;
-
-	const struct cpu_intel_haswell_config *conf = lapic->chip_info;
-
 	return conf->s0ix_enable;
 }
 
-static void generate_C_state_entries(void)
+static void generate_C_state_entries(const struct device *dev)
 {
 	acpi_cstate_t acpi_cstate_map[3] = {0};
 
 	const int *acpi_cstates;
 
-	if (is_s0ix_enabled())
+	if (is_s0ix_enabled(dev))
 		acpi_cstates = cstate_set_s0ix;
 	else if (haswell_is_ult())
 		acpi_cstates = cstate_set_lp;
@@ -352,7 +346,7 @@ void generate_cpu_entries(const struct device *device)
 				coreID - 1, cores_per_package);
 
 			/* Generate C-state tables */
-			generate_C_state_entries();
+			generate_C_state_entries(device);
 
 			/* Generate T-state tables */
 			generate_T_state_entries(

src/cpu/intel/haswell/chip.h

@@ -1,8 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* Magic value used to locate this chip in the device tree */
-#define SPEEDSTEP_APIC_MAGIC 0xACAC
-
 #include <stdbool.h>
 #include <stdint.h>
 

src/cpu/intel/haswell/haswell_init.c

@@ -172,18 +172,16 @@ static int pcode_mailbox_write(u32 command, u32 data)
 	return 0;
 }
 
+static struct device *cpu_cluster;
+
 static void initialize_vr_config(void)
 {
 	struct cpu_vr_config vr_config = { 0 };
 	msr_t msr;
 
-	const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+	/* Make sure your devicetree has the cpu_cluster below chip cpu/intel/haswell! */
-
+	const struct cpu_intel_haswell_config *conf = cpu_cluster->chip_info;
-	if (lapic && lapic->chip_info) {
+	vr_config = conf->vr_config;
-		const struct cpu_intel_haswell_config *conf = lapic->chip_info;
-
-		vr_config = conf->vr_config;
-	}
 
 	printk(BIOS_DEBUG, "Initializing VR config.\n");
 
@@ -448,18 +446,12 @@ static void configure_c_states(void)
 	wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
 }
 
-static void configure_thermal_target(void)
+static void configure_thermal_target(struct device *dev)
 {
-	struct cpu_intel_haswell_config *conf;
+	/* Make sure your devicetree has the cpu_cluster below chip cpu/intel/haswell! */
-	struct device *lapic;
+	struct cpu_intel_haswell_config *conf = dev->bus->dev->chip_info;
 	msr_t msr;
 
-	/* Find pointer to CPU configuration */
-	lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
-	if (!lapic || !lapic->chip_info)
-		return;
-	conf = lapic->chip_info;
-
 	/* Set TCC activation offset if supported */
 	msr = rdmsr(MSR_PLATFORM_INFO);
 	if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
@@ -551,7 +543,7 @@ static void cpu_core_init(struct device *cpu)
 	configure_misc();
 
 	/* Thermal throttle activation offset */
-	configure_thermal_target();
+	configure_thermal_target(cpu);
 
 	/* Enable Direct Cache Access */
 	configure_dca_cap();
@@ -638,6 +630,7 @@ static const struct mp_ops mp_ops = {
 
 void mp_init_cpus(struct bus *cpu_bus)
 {
+	cpu_cluster = cpu_bus->dev;
 	/* TODO: Handle mp_init_with_smm failure? */
 	mp_init_with_smm(cpu_bus, &mp_ops);
 }

src/mainboard/asrock/b85m_pro4/devicetree.cb

@@ -3,12 +3,8 @@ chip northbridge/intel/haswell
 	# This mainboard has VGA
 	register "gpu_ddi_e_connected" = "1"
 
-	device cpu_cluster 0 on
+	chip cpu/intel/haswell
-		ops haswell_cpu_bus_ops
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
 	end
 
 	device domain 0 on

src/mainboard/asrock/h81m-hds/devicetree.cb

@@ -3,12 +3,8 @@
 chip northbridge/intel/haswell
 	register "gpu_ddi_e_connected" = "1"
 
-	device cpu_cluster 0 on
+	chip cpu/intel/haswell
-		ops haswell_cpu_bus_ops
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
 	end
 
 	device domain 0 on

src/mainboard/google/auron/devicetree.cb

@@ -14,14 +14,10 @@ chip soc/intel/broadwell
 
 	register "ec_present" = "true"
 
-	device cpu_cluster 0 on
+	chip cpu/intel/haswell
-		ops broadwell_cpu_bus_ops
+		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
-		chip cpu/intel/haswell
-			register "s0ix_enable" = "1"
 
-			device lapic 0 on end
+		register "s0ix_enable" = "1"
-			device lapic 0xacac off end
-		end
 	end
 
 	device domain 0 on

src/mainboard/google/auron/variants/buddy/overridetree.cb

@@ -11,13 +11,10 @@ chip soc/intel/broadwell
 
 	register "dq_pins_interleaved" = "true"
 
-	device cpu_cluster 0 on
+	chip cpu/intel/haswell
-		chip cpu/intel/haswell
+		device cpu_cluster 0 on end
-			register "s0ix_enable" = "0"
 
-			device lapic 0 on end
+		register "s0ix_enable" = "0"
-			device lapic 0xacac off end
-		end
 	end
 
 	device domain 0 on

src/mainboard/google/auron/variants/samus/overridetree.cb

@@ -12,19 +12,17 @@ chip soc/intel/broadwell
 		.backlight_pwm_hz	= 200,
 	}"
 
-	device cpu_cluster 0 on
+	chip cpu/intel/haswell
-		chip cpu/intel/haswell
+		device cpu_cluster 0 on end
-			# Disable S0ix for now
-			register "s0ix_enable" = "0"
 
-			register "vr_config" = "{
+		# Disable S0ix for now
-				.slow_ramp_rate_set    = 3,
+		register "s0ix_enable" = "0"
-				.slow_ramp_rate_enable = true,
+
-			}"
+		register "vr_config" = "{
+			.slow_ramp_rate_set    = 3,
+			.slow_ramp_rate_enable = true,
+		}"
 
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
 	end
 
 	device domain 0 on

src/mainboard/google/beltino/devicetree.cb

@@ -13,13 +13,8 @@ chip northbridge/intel/haswell
 
 	register "usb_xhci_on_resume" = "true"
 
-	device cpu_cluster 0 on
+	chip cpu/intel/haswell
-		ops haswell_cpu_bus_ops
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			# Magic APIC ID to locate this chip
-			device lapic 0xACAC off end
-		end
 	end
 
 	device domain 0 on

src/mainboard/google/jecht/devicetree.cb

@@ -11,12 +11,8 @@ chip soc/intel/broadwell
 
 	register "dq_pins_interleaved" = "true"
 
-	device cpu_cluster 0 on
+	chip cpu/intel/haswell
-		ops broadwell_cpu_bus_ops
+		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
 	end
 
 	device domain 0 on

src/mainboard/google/slippy/devicetree.cb

@@ -15,13 +15,8 @@ chip northbridge/intel/haswell
 
 	register "usb_xhci_on_resume" = "true"
 
-	device cpu_cluster 0 on
+	chip cpu/intel/haswell
-		ops haswell_cpu_bus_ops
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			# Magic APIC ID to locate this chip
-			device lapic 0xACAC off end
-		end
 	end
 
 	device domain 0 on

src/mainboard/hp/folio_9480m/devicetree.cb

@@ -13,12 +13,8 @@ chip northbridge/intel/haswell
 		.backlight_pwm_hz	= 200,
 	}"
 	register "usb_xhci_on_resume" = "true"
-	device cpu_cluster 0 on
+	chip cpu/intel/haswell
-		ops haswell_cpu_bus_ops
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
 	end
 	device domain 0 on
 		ops haswell_pci_domain_ops

src/mainboard/intel/baskingridge/devicetree.cb

@@ -11,13 +11,8 @@ chip northbridge/intel/haswell
 	# Enable DVI Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
-	device cpu_cluster 0 on
+	chip cpu/intel/haswell
-		ops haswell_cpu_bus_ops
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			# Magic APIC ID to locate this chip
-			device lapic 0xACAC off end
-		end
 	end
 
 	device domain 0 on

src/mainboard/intel/wtm2/devicetree.cb

@@ -9,12 +9,8 @@ chip soc/intel/broadwell
 	# Enable DVI Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
-	device cpu_cluster 0 on
+	chip cpu/intel/haswell
-		ops broadwell_cpu_bus_ops
+		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
 	end
 	device domain 0 on
 		ops broadwell_pci_domain_ops

src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb

@@ -13,12 +13,8 @@ chip northbridge/intel/haswell
 		.backlight_pwm_hz	= 220,
 	}"
 	register "ec_present" = "true"
-	device cpu_cluster 0 on
+	chip cpu/intel/haswell
-		ops haswell_cpu_bus_ops
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
 	end
 	device domain 0 on
 		ops haswell_pci_domain_ops

src/mainboard/lenovo/haswell/variants/w541/devicetree.cb

@@ -13,12 +13,8 @@ chip northbridge/intel/haswell
 		.backlight_pwm_hz	= 220,
 	}"
 	register "ec_present" = "true"
-	device cpu_cluster 0 on
+	chip cpu/intel/haswell
-		ops haswell_cpu_bus_ops
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
 	end
 	device domain 0 on
 		ops haswell_pci_domain_ops

src/mainboard/msi/h81m-p33/devicetree.cb

@@ -2,12 +2,8 @@
 
 chip northbridge/intel/haswell
 	register "gpu_ddi_e_connected" = "1"
-	device cpu_cluster 0 on
+	chip cpu/intel/haswell
-		ops haswell_cpu_bus_ops
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
 	end
 	device domain 0 on
 		ops haswell_pci_domain_ops

src/mainboard/purism/librem_bdw/devicetree.cb

@@ -20,12 +20,8 @@ chip soc/intel/broadwell
 		.backlight_pwm_hz	= 200,
 	}"
 
-	device cpu_cluster 0 on
+	chip cpu/intel/haswell
-		ops broadwell_cpu_bus_ops
+		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
 	end
 	device domain 0 on
 		ops broadwell_pci_domain_ops

src/mainboard/supermicro/x10slm-f/devicetree.cb

@@ -2,12 +2,8 @@
 
 chip northbridge/intel/haswell
 
-	device cpu_cluster 0 on
+	chip cpu/intel/haswell
-		ops haswell_cpu_bus_ops
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
 	end
 
 	device domain 0 on

src/northbridge/intel/haswell/northbridge.c

@@ -536,7 +536,6 @@ static struct device_operations mc_ops = {
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= northbridge_init,
 	.final			= northbridge_final,
-	.acpi_fill_ssdt		= generate_cpu_entries,
 	.ops_pci		= &pci_dev_ops_pci,
 };
 
@@ -561,6 +560,7 @@ struct device_operations haswell_cpu_bus_ops = {
 	.read_resources   = noop_read_resources,
 	.set_resources    = noop_set_resources,
 	.init             = mp_cpu_bus_init,
+	.acpi_fill_ssdt   = generate_cpu_entries,
 };
 
 struct chip_operations northbridge_intel_haswell_ops = {

src/soc/intel/broadwell/northbridge.c

@@ -398,7 +398,6 @@ static void systemagent_init(struct device *dev)
 
 static struct device_operations systemagent_ops = {
 	.read_resources   = systemagent_read_resources,
-	.acpi_fill_ssdt   = generate_cpu_entries,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = systemagent_init,
@@ -432,6 +431,7 @@ struct device_operations broadwell_cpu_bus_ops = {
 	.read_resources   = noop_read_resources,
 	.set_resources    = noop_set_resources,
 	.init             = mp_cpu_bus_init,
+	.acpi_fill_ssdt   = generate_cpu_entries,
 };
 
 static void broadwell_init_pre_device(void *chip_info)