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Exynos5420: Fix up the i2c driver for use with the TPM driver 

The TPM driver expects to call i2c_read with zero address length. The i2c
driver wasn't prepared to handle that particularly in the case of reads
because it expected to send an address before switching over to read mode for
the data. This change also fixes up the read and write calls to consistently
be read32 and write32 instead of readl and writel.

Change-Id: I33dee89b83d4cd9d3e1b90e84b40e761bb8d4de4
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/175966
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit cf686269424ea938d6f953d0f76103182eb71297)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6857
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Gabe Black 2013-11-06 11:21:48 -08:00 committed by Isaac Christensen
parent 9b47231d2e
commit dda0e66d9c
1 changed files with 15 additions and 13 deletions
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12
src/soc/samsung/exynos5420/i2c.c
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@ -210,7 +210,7 @@ static int WaitForXfer(struct s3c24x0_i2c *i2c)
static void ReadWriteByte(struct s3c24x0_i2c *i2c) static void ReadWriteByte(struct s3c24x0_i2c *i2c)
{ {
writel(read32(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); write32(read32(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
} }
static void i2c_ch_init(struct s3c24x0_i2c_bus *bus, int speed, int slaveadd) static void i2c_ch_init(struct s3c24x0_i2c_bus *bus, int speed, int slaveadd)
@ -318,7 +318,7 @@ static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus,
write32(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl); write32(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl);
/* i2c_conf configure */ /* i2c_conf configure */
write32(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf); write32(read32(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf);
} }
/* SW reset for the high speed bus */ /* SW reset for the high speed bus */
@ -484,8 +484,9 @@ static int hsi2c_read(struct exynos5_hsi2c *i2c,
/* chip address */ /* chip address */
write32(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr); write32(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr);
if (alen) {
/* usi_ctl enable i2c func, master write configure */ /* usi_ctl enable i2c func, master write configure */
write32((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), write32(HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER,
&i2c->usi_ctl); &i2c->usi_ctl);
/* auto_conf */ /* auto_conf */
@ -496,6 +497,7 @@ static int hsi2c_read(struct exynos5_hsi2c *i2c,
hsi2c_wait_for_transfer(i2c) != 1) { hsi2c_wait_for_transfer(i2c) != 1) {
return -1; return -1;
} }
}
/* usi_ctl enable i2c func, master WRITE configure */ /* usi_ctl enable i2c func, master WRITE configure */
write32((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), write32((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
@ -542,7 +544,7 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c,
timer_monotonic_get(&current); timer_monotonic_get(&current);
end = current; end = current;
mono_time_add_usecs(&end, I2C_TIMEOUT_MS * 1000); mono_time_add_usecs(&end, I2C_TIMEOUT_MS * 1000);
while (readl(&i2c->iicstat) & I2CSTAT_BSY) { while (read32(&i2c->iicstat) & I2CSTAT_BSY) {
if (!mono_time_before(&current, &end)){ if (!mono_time_before(&current, &end)){
printk(BIOS_ERR, "%s timed out\n", __func__); printk(BIOS_ERR, "%s timed out\n", __func__);
return I2C_NOK_TOUT; return I2C_NOK_TOUT;
@ -607,7 +609,7 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c,
while ((i < data_len) && (result == I2C_OK)) { while ((i < data_len) && (result == I2C_OK)) {
/* disable ACK for final READ */ /* disable ACK for final READ */
if (i == data_len - 1) if (i == data_len - 1)
write32(readl(&i2c->iiccon) write32(read32(&i2c->iiccon)
& ~I2CCON_ACKGEN, & ~I2CCON_ACKGEN,
&i2c->iiccon); &i2c->iiccon);
ReadWriteByte(i2c); ReadWriteByte(i2c);