From ddb64d33a0c4e005a30092960953707b12fd78c6 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 3 Jul 2017 21:35:58 +0200 Subject: [PATCH] sb/intel/i82801gx: Add whitespace around '<<' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I8ea8fdb031c09aac9ed4a0705c3204f87aadb565 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/20457 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Martin Roth --- src/southbridge/intel/i82801gx/smi.c | 4 ++-- src/southbridge/intel/i82801gx/smihandler.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c index 45fcb10307..17a81c1757 100644 --- a/src/southbridge/intel/i82801gx/smi.c +++ b/src/southbridge/intel/i82801gx/smi.c @@ -232,9 +232,9 @@ static u32 reset_tco_status(void) reg32 = inl(tcobase + 0x04); /* set status bits are cleared by writing 1 to them */ - outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS + outl(reg32 & ~(1 << 18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS if (reg32 & (1 << 18)) - outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS + outl(reg32 & (1 << 18), tcobase + 0x04); // clear BOOT_STS return reg32; } diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 6bd9517f42..6075db9e8b 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -248,9 +248,9 @@ static u32 reset_tco_status(void) reg32 = inl(tcobase + 0x04); /* set status bits are cleared by writing 1 to them */ - outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS + outl(reg32 & ~(1 << 18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS if (reg32 & (1 << 18)) - outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS + outl(reg32 & (1 << 18), tcobase + 0x04); // clear BOOT_STS return reg32; }