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soc/intel/cannonlake: Configure SPI CS parameters in FSP UPD. 

When FSP UPD parameters are configured, also configure the GSPI CS lines
appropriately.  GSPI driver assumes CS0 is the CS signal to use.

BUG=b:130329260
BRANCH=None
TEST=Boot Kohaku, TPM communcation still functional.

Change-Id: Ic816395b7d198a52c704e6cabcb56889150b741c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32791
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak 2019-05-15 08:42:20 -06:00 committed by Patrick Georgi
parent 334e8360ef
commit ddbf2c4af0
1 changed files with 43 additions and 0 deletions
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43
src/soc/intel/cannonlake/fsp_params.c
View File

@ -119,6 +119,28 @@ static void ignore_gbe_ltr(void)
write8(pmcbase + LTR_IGN, reg8);
}
static void configure_gspi_cs(int idx, const config_t *config,
uint8_t *polarity, uint8_t *enable,
uint8_t *defaultcs)
{
struct spi_cfg cfg;
/* If speed_mhz is set, infer that the port should be configured */
if (config->common_soc_config.gspi[idx].speed_mhz != 0) {
if (gspi_get_soc_spi_cfg(idx, &cfg) == 0) {
if (cfg.cs_polarity == SPI_POLARITY_LOW)
*polarity = 0;
else
*polarity = 1;
if (defaultcs != NULL)
*defaultcs = 0;
if (enable != NULL)
*enable = 1;
}
}
}
/* UPD parameters to be initialized before SiliconInit */
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
@ -357,6 +379,27 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Unlock all GPIO pads */
tconfig->PchUnlockGpioPads = config->PchUnlockGpioPads;
/*
* GSPI Chip Select parameters
* The GSPI driver assumes that CS0 is the used chip-select line,
* therefore only CS0 is configured below.
*/
#if CONFIG(SOC_INTEL_COMETLAKE)
configure_gspi_cs(0, config, &params->SerialIoSpi0CsPolarity[0],
&params->SerialIoSpi0CsEnable[0],
&params->SerialIoSpiDefaultCsOutput[0]);
configure_gspi_cs(1, config, &params->SerialIoSpi1CsPolarity[0],
&params->SerialIoSpi1CsEnable[0],
&params->SerialIoSpiDefaultCsOutput[1]);
configure_gspi_cs(2, config, &params->SerialIoSpi2CsPolarity[0],
&params->SerialIoSpi2CsEnable[0],
&params->SerialIoSpiDefaultCsOutput[2]);
#else
for (i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++)
configure_gspi_cs(i, config,
&params->SerialIoSpiCsPolarity[0], NULL, NULL);
#endif
}
/* Mainboard GPIO Configuration */