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vc/amd/agesa/f16kb: raise the UDIMM Freq limit 1333MT/s values to 1600MT/s 

AMD f16kb boards are perfectly capable of working at 1600MT/s RAM speeds
even with two DDR3 UDIMM modules per channel. AM1I-A only supports a
single-channel operation, with at most two DIMMs per channel, so raising
these limit values is required to let it and similar boards run faster.

Successfully tested on AM1I-A and two Crucial BLT8G3D1869DT1TX0 UDIMMs,
together with related AMD_XMP changes - also required to get a 1600MT/s
with this set of modules which have only 1333MT/s at JEDEC part of SPD.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I2a9da4e594ab3dc38b5ba87520633cbd01c9ce01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44461
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mike Banon 2020-08-14 16:25:10 +03:00 committed by Angel Pons
parent 86ea251ba0
commit ddc2a30737
1 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c
View File

@ -92,8 +92,8 @@ STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqKBUDIMM6L[] = {
{{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 1, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
};
CONST PSC_TBL_ENTRY KBMaxFreqTblEntU6L = {
{PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
@ -111,8 +111,8 @@ STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqKBMicroSrvUDIMM6L[] = {
{{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 1, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
};
CONST PSC_TBL_ENTRY KBMaxFreqTblEntMicroSrvU6L = {
{PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
@ -130,8 +130,8 @@ STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqKBUDIMM4L[] = {
{{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 1, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
};
CONST PSC_TBL_ENTRY KBMaxFreqTblEntU4L = {
{PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},