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mb/asus/kfsn4-dre: Use common pnp_{enter,exit} functions 

Change-Id: I4b0577bf3c00307733a1096749c1835d86764f29
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Elyes HAOUAS 2018-08-06 10:40:07 +02:00 committed by Felix Held
parent e051dc07f5
commit ddcf5a05e3
1 changed files with 2 additions and 4 deletions
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6
src/mainboard/asus/kfsn4-dre/romstage.c
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@ -343,9 +343,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Initialize GPIO */ /* Initialize GPIO */
/* Access SuperIO GPI03 logical device */ /* Access SuperIO GPI03 logical device */
uint16_t port = GPIO3_DEV >> 8; pnp_enter_conf_state(GPIO3_DEV);
outb(0x87, port);
outb(0x87, port);
pnp_set_logical_device(GPIO3_DEV); pnp_set_logical_device(GPIO3_DEV);
/* Set GP37 (power LED) to output */ /* Set GP37 (power LED) to output */
pnp_write_config(GPIO3_DEV, 0xf0, 0x7f); pnp_write_config(GPIO3_DEV, 0xf0, 0x7f);
@ -355,7 +353,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
uint8_t cr2c = pnp_read_config(GPIO3_DEV, 0x2c); uint8_t cr2c = pnp_read_config(GPIO3_DEV, 0x2c);
pnp_write_config(GPIO3_DEV, 0x2c, (cr2c & 0xf3) | 0x04); pnp_write_config(GPIO3_DEV, 0x2c, (cr2c & 0xf3) | 0x04);
/* Restore default SuperIO access */ /* Restore default SuperIO access */
outb(0xaa, port); pnp_exit_conf_state(GPIO3_DEV);
} }
/** /**