mb/supermicro/x11-lga1151-series: restructure and clean up devicetree
Drop zero-value devicetree options and move PcieRpEnable options down to the corresponding devices. Test: built with TIMELESS=1; binaries remain identical Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I9285d786e973621a732e2627c734adc930e54207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Michael Niewöhner
parent
84fde762e7
commit
ddd44f4fe9
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@ -1,10 +1,6 @@
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chip soc/intel/skylake
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register "deep_s5_enable_ac" = "0"
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register "deep_s5_enable_dc" = "0"
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# FSP Configuration
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register "ScsEmmcHs400Enabled" = "0"
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register "SkipExtGfxScan" = "1"
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register "SaGv" = "SaGv_Disabled"
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@ -22,20 +18,6 @@ chip soc/intel/skylake
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[7] = 1, \
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}"
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register "SataPortsDevSlp" = "{\
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[0] = 0, \
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[1] = 0, \
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[2] = 0, \
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[3] = 0, \
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[4] = 0, \
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[5] = 0, \
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[6] = 0, \
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[7] = 0, \
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}"
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# superspeed_inter-chip_supplement (SSIC) disabled
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register "SsicPortEnable" = "0"
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# LPC
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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@ -46,9 +28,6 @@ chip soc/intel/skylake
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register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S"
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register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S"
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# No extra VR mailbox command
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register "SendVrMbxCmd" = "0"
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# Lock Down
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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@ -11,19 +11,6 @@ chip soc/intel/skylake
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register "gen1_dec" = "0x007c0a01" # Super IO SWC
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register "gen2_dec" = "0x000c0ca1" # IPMI KCS
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# PCIe configuration
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# Enable JPCIE1
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register "PcieRpEnable[0]" = "1"
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# Enable ASpeed PCI bridge
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register "PcieRpEnable[2]" = "1"
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# Enable X550T (10GbE)
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register "PcieRpEnable[4]" = "1"
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# Enable M.2
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register "PcieRpEnable[8]" = "1"
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# FIXME: find out why FSP crashes without this
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register "PchHdaVcType" = "Vc1"
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@ -66,9 +53,11 @@ chip soc/intel/skylake
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device domain 0 on
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device pci 01.0 on end # unused
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device pci 01.1 on # PCIE Slot (JPCIE1)
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register "PcieRpEnable[0]" = "1"
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smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X"
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end
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device pci 1c.0 on # PCI Express Port 1 (Slot JPCIE1)
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register "PcieRpEnable[2]" = "1"
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smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X"
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end
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device pci 1c.2 on # PCI Express Port 3
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@ -77,10 +66,12 @@ chip soc/intel/skylake
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end
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end
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device pci 1c.4 on # PCI Express Port 5
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register "PcieRpEnable[4]" = "1"
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device pci 00.0 on end # 10GbE
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device pci 00.1 on end # 10GbE
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end
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device pci 1d.0 on # PCI Express Port 9
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register "PcieRpEnable[8]" = "1"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X"
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end
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device pci 1f.0 on # LPC Interface
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@ -11,13 +11,6 @@ chip soc/intel/skylake
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register "gen1_dec" = "0x007c0a01" # Super IO SWC
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register "gen2_dec" = "0x000c0ca1" # IPMI KCS
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# PCIe configuration
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register "PcieRpEnable[0]" = "1" # Enable PCH PCIe Port 1 / PCH SLOT4
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register "PcieRpEnable[4]" = "1" # Enable PCH PCIe Port 5 / PCH SLOT5
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register "PcieRpEnable[8]" = "1" # Enable PCH PCIe Port 9 / GbE 1
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register "PcieRpEnable[9]" = "1" # Enable PCH PCIe Port 10 / GbE 2
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register "PcieRpEnable[10]" = "1" # Enable PCH PCIe Port 11 / Aspeed 2400 VGA
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# USB configuration
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# USB0/1
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register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
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@ -58,18 +51,23 @@ chip soc/intel/skylake
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smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT7 PCI-E 3.0 X8" "SlotDataBusWidth8X"
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end
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device pci 1c.0 on # PCH PCIe Port 1 / PCIe Slot 4 (JPCIE4)
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register "PcieRpEnable[0]" = "1"
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smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
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end
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device pci 1c.4 on # PCH PCIe Port 5 / PCIe Slot 5 (JPCIE5)
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register "PcieRpEnable[4]" = "1"
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smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
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end
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device pci 1d.0 on # PCH PCIe Port 9
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register "PcieRpEnable[8]" = "1"
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device pci 00.0 on end # GbE 1
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end
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device pci 1d.1 on # PCH PCIe Port 10
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register "PcieRpEnable[9]" = "1"
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device pci 00.1 on end # GbE 2
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end
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device pci 1d.2 on # PCH PCIe Port 11
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register "PcieRpEnable[10]" = "1"
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device pci 00.0 on # Aspeed PCI Bridge
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device pci 00.0 on end # Aspeed 2400 VGA
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end
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