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Intel 82801Gx: LPC: Unify I/O APIC setup 

Remove local copies of reading and writing I/O APIC registers by
using already available functions.

This change is similar to

    commit db4f875a41
    Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Date:   Tue Jan 31 17:24:12 2012 +0200

        IOAPIC: Divide setup_ioapic() in two parts.

        Reviewed-on: http://review.coreboot.org/300

and

    commit e614353194
    Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Date:   Tue Feb 26 17:24:41 2013 +0200

        Unify setting 82801a/b/c/d IOAPIC ID

        Reviewed-on: http://review.coreboot.org/2532

and uses `io_apic_read()` and `io_apic_write()` too.

As commented by Aaron Durbin, a separate `i82801gx_enable_acpi()` is
not needed: “The existing code path *in this file* is about enabling
the io apic.” [1].

[1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c

Change-Id: I104a2d9c2898da14d26f8f2992d5a065ad640356
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3181
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Paul Menzel 2013-04-23 14:40:23 +02:00 committed by Aaron Durbin
parent 1b3e176468
commit ddddf15ca3
1 changed files with 14 additions and 28 deletions
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42
src/southbridge/intel/i82801gx/lpc.c
View File

@ -39,37 +39,23 @@
typedef struct southbridge_intel_i82801gx_config config_t; typedef struct southbridge_intel_i82801gx_config config_t;
static void i82801gx_enable_apic(struct device *dev) /**
{ * Set miscellanous static southbridge features.
int i; *
u32 reg32; * @param dev PCI device with I/O APIC control registers
volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
/* Enable ACPI I/O and power management.
* Set SCI IRQ to IRQ9
*/ */
static void i82801gx_enable_ioapic(struct device *dev)
{
/* Enable ACPI I/O range decode */
pci_write_config8(dev, ACPI_CNTL, ACPI_EN); pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
*ioapic_index = 0; set_ioapic_id(IO_APIC_ADDR, 0x02);
*ioapic_data = (2 << 24);
*ioapic_index = 0; /*
reg32 = *ioapic_data; * Select Boot Configuration register (0x03) and
printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); * use Processor System Bus (0x01) to deliver interrupts.
if (reg32 != (2 << 24)) */
die("APIC Error\n"); io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
for (i=0; i<3; i++) {
*ioapic_index = i;
printk(BIOS_SPEW, " reg 0x%04x:", i);
reg32 = *ioapic_data;
printk(BIOS_SPEW, " 0x%08x\n", reg32);
}
*ioapic_index = 3; /* Select Boot Configuration register. */
*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
} }
static void i82801gx_enable_serial_irqs(struct device *dev) static void i82801gx_enable_serial_irqs(struct device *dev)
@ -422,7 +408,7 @@ static void lpc_init(struct device *dev)
pci_write_config16(dev, PCI_COMMAND, 0x000f); pci_write_config16(dev, PCI_COMMAND, 0x000f);
/* IO APIC initialization. */ /* IO APIC initialization. */
i82801gx_enable_apic(dev); i82801gx_enable_ioapic(dev);
i82801gx_enable_serial_irqs(dev); i82801gx_enable_serial_irqs(dev);