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google/reef: Tune eMMC DLL settings for reef evt 

Apply eMMC tuned DLL settings for reef evt.
Modify comments to avoid replicating info.
Add EDS reference.

BUG=chrome-os-partner:55648
BRANCH=none
TEST=Verify that reef evt boots to OS from eMMC.

Change-Id: If3bf51f3b7d38320f504ea6fbecf7c188a94ae5c
Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Reviewed-on: https://review.coreboot.org/16296
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Chiranjeevi Rapolu 2016-08-22 10:55:10 -07:00 committed by Duncan Laurie
parent 67e4df8b65
commit dde073829f
1 changed files with 25 additions and 21 deletions
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46
src/mainboard/google/reef/devicetree.cb
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@ -6,30 +6,34 @@ chip soc/intel/apollolake
register "pcie_rp4_clkreq_pin" = "0" # wifi/bt register "pcie_rp4_clkreq_pin" = "0" # wifi/bt
# EMMC TX DATA Delay 1# # EMMC TX DATA Delay 1
# 0x0C[14:8] stands for 12*125 = 1500 pSec delay for HS400 # Refer to EDS-Vol2-22.3.
# 0x11[6:0] stands for 17*125 = 2125 pSec delay for SDR104/HS200 # [14:8] steps of delay for HS400, each 125ps.
register "emmc_tx_data_cntl1" = "0x0C11" # HS400 required # [6:0] steps of delay for SDR104/HS200, each 125ps.
register "emmc_tx_data_cntl1" = "0x0C16"
# EMMC TX DATA Delay 2# # EMMC TX DATA Delay 2
# 0x00[30:24] stands for 0*125 = no delay for SDR50 # Refer to EDS-Vol2-22.3.
# 0x2B[22:16] stands for 43*125 = 5375 pSec delay for DDR50 # [30:24] steps of delay for SDR50, each 125ps.
# 0x29[14:8] stands for 41*125 = 5125 pSec delay for SDR25/HS50 # [22:16] steps of delay for DDR50, each 125ps.
# 0x29[6:0] stands for 41*125 = 5125 pSec delay for SDR12 # [14:8] steps of delay for SDR25/HS50, each 125ps.
register "emmc_tx_data_cntl2" = "0x002B2929" # [6:0] steps of delay for SDR12, each 125ps.
register "emmc_tx_data_cntl2" = "0x28162828"
# EMMC RX CMD/DATA Delay 1# # EMMC RX CMD/DATA Delay 1
# 0x00[30:24] stands for 0*125 = no delay for SDR50 # Refer to EDS-Vol2-22.3.
# 0x12[22:16] stands for 18*125 = 2250 pSec delay for DDR50 # [30:24] steps of delay for SDR50, each 125ps.
# 0x57[14:8] stands for 87*125 = 10875 pSec delay for SDR25/HS50 # [22:16] steps of delay for DDR50, each 125ps.
# 0x3B[6:0] stands for 59*125= 7375 pSec delay for SDR12 # [14:8] steps of delay for SDR25/HS50, each 125ps.
register "emmc_rx_cmd_data_cntl1" = "0x0012573B" # [6:0] steps of delay for SDR12, each 125ps.
register "emmc_rx_cmd_data_cntl1" = "0x00181717"
# EMMC RX CMD/DATA Delay 2# # EMMC RX CMD/DATA Delay 2
# 0x01[17:16] stands for Rx Clock before Output Buffer # Refer to EDS-Vol2-22.3.
# 0x00[14:8] stands for 0 delay for Auto Tuning Mode # [17:16] stands for Rx Clock before Output Buffer
# 0x1C[6:0] stands for 28*125 = 3500 pSec delay for HS200 # [14:8] steps of delay for Auto Tuning Mode, each 125ps.
register "emmc_rx_cmd_data_cntl2" = "0x1001C" # [6:0] steps of delay for HS200, each 125ps.
register "emmc_rx_cmd_data_cntl2" = "0x10008"
# Enable DPTF # Enable DPTF
register "dptf_enable" = "1" register "dptf_enable" = "1"