src/soc/intel/jasperlake: Update SD card ACPI device

1. Add _DSM method
2. Add support to turn on/off the power enable signal in _PS0/_PS3
   methods.

Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I4f944caa535bdc946eef1e0f518fe3ee344187b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>

src/soc/intel/jasperlake/acpi/scs.asl

@@ -71,6 +71,7 @@ Scope (\_SB.PCI0) {
 		Name (_ADR, 0x00140005)
 		Name (_DDN, "SD Controller")
 		Name (TEMP, 0)
+		Name (DSUU, ToUUID("f6c13ea5-65cd-461f-ab7a-29f7e8d5bd61"))
 
 		OperationRegion (SDPC, PCI_Config, 0x00, 0x100)
 		Field (SDPC, WordAcc, NoLock, Preserve)
@@ -82,6 +83,65 @@ Scope (\_SB.PCI0) {
 			PGEN, 1,	/* PG_ENABLE */
 		}
 
+		/*
+		 * _DSM x86 Device Specific Method
+		 * Arg0: UUID Unique function identifier
+		 * Arg1: Integer Revision Level
+		 * Arg2: Integer Function Index (0 = Return Supported Functions)
+		 * Arg3: Package Parameters
+		 */
+		Method (_DSM, 4)
+		{
+			If (Arg0 == DSUU) {
+				/* Check the revision */
+				If (Arg1 >= 0) {
+					/*
+					 * Function Index 0 the return value is a buffer containing
+					 * one bit for each function index, starting with zero.
+					 * Bit 0 - Indicates whether there is support for any
+					 *         functions other than function 0.
+					 * Bit 1 - Indicates support to clear power control register
+					 * Bit 2 - Indicates support to set power control register
+					 * Bit 3 - Indicates support to set 1.8V signalling
+					 * Bit 4 - Indicates support to set 3.3V signalling
+					 * Bit 5 - Indicates support for HS200 mode
+					 * Bit 6 - Indicates support for HS400 mode
+					 * Bit 9 - Indicates eMMC I/O Driver Strength
+					 */
+					/*
+					 * For SD we have to support functions to
+					 * set 1.8V signalling and 3.3V signalling [BIT4, BIT3]
+					 */
+					If (Arg2 == 0) {
+						Return (Buffer () { 0x19 })
+					}
+					/*
+					 * Function Index 3: Set 1.8v signalling.
+					 * We put a sleep of 100ms in this method to
+					 * work around a known issue with detecting
+					 * UHS SD card on PCH. This is to compensate
+					 * for the SD VR slowness.
+					 */
+					If (Arg2 == 3) {
+						Sleep (100)
+						Return(Buffer () { 0x00 })
+					}
+					/*
+					 * Function Index 4: Set 3.3v signalling.
+					 * We put a sleep of 100ms in this method to
+					 * work around a known issue with detecting
+					 * UHS SD card on PCH. This is to compensate
+					 * for the SD VR slowness.
+					 */
+					If (Arg2 == 4) {
+						Sleep (100)
+						Return(Buffer () { 0x00 })
+					}
+				}
+			}
+			Return(Buffer() { 0x0 })
+		}
+
 		Method(_INI)
 		{
 			/* Clear register 0x1C20/0x4820 */
@@ -98,6 +158,9 @@ Scope (\_SB.PCI0) {
 			/* Set Power State to D0 */
 			PMCR = PMCR & 0xFFFC
 			TEMP = PMCR
+
+			/* Change pad mode to Native */
+			GPMO(SD_PWR_EN_PIN, 0x1)
 		}
 
 		Method (_PS3, 0, Serialized)
@@ -107,6 +170,15 @@ Scope (\_SB.PCI0) {
 			/* Set Power State to D3 */
 			PMCR = PMCR | 0x0003
 			TEMP = PMCR
+
+			/* Change pad mode to GPIO control */
+			GPMO(SD_PWR_EN_PIN, 0x0)
+
+			/* Enable Tx Buffer */
+			GTXE(SD_PWR_EN_PIN, 0x1)
+
+			/* Drive TX to zero */
+			CTXS(SD_PWR_EN_PIN)
 		}
 
 		Device (CARD)

src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h

@@ -24,6 +24,7 @@
 
 #define GPIO_NUM_GROUPS		12
 #define GPIO_MAX_NUM_PER_GROUP	24
+#define SD_PWR_EN_PIN		GPP_H1
 
 /*
  * GPIOs are ordered monotonically increasing to match ACPI/OS driver.