mb/google/zork: Split devicetree between baseboards
Split zork baseboard devicetree between dalboz and trembyle. The devicetree is simply duplicated, no other changes in this commit. BUG=b:158096224 TEST=Build coreboot for zork Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I5b26770790092c69db9567fa4337edd21a6ed809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Rob Barnes
Patrick Georgi
parent
51c6d4429c
commit
ddeba9f196
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@ -81,7 +81,8 @@ config MAINBOARD_PART_NUMBER
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config DEVICETREE
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string
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default "variants/baseboard/devicetree.cb"
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default "variants/baseboard/devicetree_trembyle.cb" if BOARD_GOOGLE_BASEBOARD_TREMBYLE
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default "variants/baseboard/devicetree_dalboz.cb" if BOARD_GOOGLE_BASEBOARD_DALBOZ
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config OVERRIDE_DEVICETREE
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string
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@ -0,0 +1,280 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip soc/amd/picasso
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# Set FADT Configuration
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register "fadt_pm_profile" = "PM_MOBILE"
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register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
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register "fadt_flags" = "ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */
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ACPI_FADT_C1_SUPPORTED |
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ACPI_FADT_SLEEP_BUTTON |
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ACPI_FADT_S4_RTC_WAKE |
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ACPI_FADT_32BIT_TIMER |
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ACPI_FADT_RESET_REGISTER |
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ACPI_FADT_SEALED_CASE |
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ACPI_FADT_PCI_EXPRESS_WAKE |
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ACPI_FADT_REMOTE_POWER_ON"
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register "acp_pin_cfg" = "I2S_PINS_I2S_TDM"
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# DMIC select GPIO for ACP machine device
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# This GPIO is used to select DMIC0 or DMIC1 by the kernel driver. It does not
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# really have a polarity since low and high control the selection of DMIC and
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# hence does not have an active polarity.
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# Kernel driver does not use the polarity field and instead treats the GPIO
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# selection as follows:
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# Set low (0) = Select DMIC0
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# Set high (1) = Select DMIC1
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register "dmic_select_gpio" = "ACPI_GPIO_OUTPUT(GPIO_67)"
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# Start : OPN Performance Configuration
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# (Configuratin that is common for all variants)
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# For the below fields, 0 indicates use SOC default
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# PROCHOT_L de-assertion Ramp Time
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register "prochot_l_deassertion_ramp_time" = "20" #mS
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# Lower die temperature limit
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register "thermctl_limit" = "100" #degrees C
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# FP5 Processor Voltage Supply PSI Currents
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register "psi0_current_limit" = "18000" #mA
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register "psi0_soc_current_limit" = "12000" #mA
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register "vddcr_soc_voltage_margin" = "0" #mV
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register "vddcr_vdd_voltage_margin" = "0" #mV
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# VRM Limits
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register "vrm_maximum_current_limit" = "0" #mA
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register "vrm_soc_maximum_current_limit" = "0" #mA
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register "vrm_current_limit" = "0" #mA
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register "vrm_soc_current_limit" = "0" #mA
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# Misc SMU settings
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register "sb_tsi_alert_comparator_mode_en" = "0"
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register "core_dldo_bypass" = "1"
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register "min_soc_vid_offset" = "0"
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register "aclk_dpm0_freq_400MHz" = "0"
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# End : OPN Performance Configuration
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register "sd_emmc_config" = "SD_EMMC_EMMC_HS400"
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register "xhci0_force_gen1" = "0"
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# Controller0 Port0 Default
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register "usb_2_port_0_tune_params" = "{
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.com_pds_tune = 0x03,
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.sq_rx_tune = 0x3,
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.tx_fsls_tune = 0x3,
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.tx_pre_emp_amp_tune = 0x03,
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.tx_pre_emp_pulse_tune = 0x0,
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.tx_rise_tune = 0x1,
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.rx_vref_tune = 0x6,
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.tx_hsxv_tune = 0x3,
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.tx_res_tune = 0x01,
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}"
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# Controller0 Port1 Default
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register "usb_2_port_1_tune_params" = "{
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.com_pds_tune = 0x03,
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.sq_rx_tune = 0x3,
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.tx_fsls_tune = 0x3,
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.tx_pre_emp_amp_tune = 0x03,
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.tx_pre_emp_pulse_tune = 0x0,
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.tx_rise_tune = 0x1,
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.rx_vref_tune = 0x6,
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.tx_hsxv_tune = 0x3,
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.tx_res_tune = 0x01,
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}"
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# Controller0 Port2 Default
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register "usb_2_port_2_tune_params" = "{
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.com_pds_tune = 0x03,
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.sq_rx_tune = 0x3,
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.tx_fsls_tune = 0x3,
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.tx_pre_emp_amp_tune = 0x03,
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.tx_pre_emp_pulse_tune = 0x0,
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.tx_rise_tune = 0x1,
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.rx_vref_tune = 0x6,
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.tx_hsxv_tune = 0x3,
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.tx_res_tune = 0x01,
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}"
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# Controller0 Port3 Default
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register "usb_2_port_3_tune_params" = "{
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.com_pds_tune = 0x03,
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.sq_rx_tune = 0x3,
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.tx_fsls_tune = 0x3,
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.tx_pre_emp_amp_tune = 0x03,
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.tx_pre_emp_pulse_tune = 0x0,
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.tx_rise_tune = 0x1,
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.rx_vref_tune = 0x6,
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.tx_hsxv_tune = 0x3,
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.tx_res_tune = 0x01,
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}"
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# Controller1 Port0 Default
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register "usb_2_port_4_tune_params" = "{
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.com_pds_tune = 0x03,
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.sq_rx_tune = 0x3,
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.tx_fsls_tune = 0x3,
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.tx_pre_emp_amp_tune = 0x02,
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.tx_pre_emp_pulse_tune = 0x0,
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.tx_rise_tune = 0x1,
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.rx_vref_tune = 0x5,
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.tx_hsxv_tune = 0x3,
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.tx_res_tune = 0x01,
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}"
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# Controller1 Port1 Default
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register "usb_2_port_5_tune_params" = "{
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.com_pds_tune = 0x03,
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.sq_rx_tune = 0x3,
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.tx_fsls_tune = 0x3,
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.tx_pre_emp_amp_tune = 0x02,
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.tx_pre_emp_pulse_tune = 0x0,
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.tx_rise_tune = 0x1,
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.rx_vref_tune = 0x5,
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.tx_hsxv_tune = 0x3,
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.tx_res_tune = 0x01,
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}"
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# SPI Configuration
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register "common_config.spi_config" = "{
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.normal_speed = SPI_SPEED_100M, /* MHz */
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.fast_speed = SPI_SPEED_100M, /* MHz */
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.altio_speed = SPI_SPEED_66M, /* MHz */
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.tpm_speed = SPI_SPEED_66M, /* MHz */
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.read_mode = SPI_READ_MODE_DUAL122,
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}"
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# eSPI Configuration
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register "common_config.espi_config" = "{
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.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN,
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.generic_io_range[0] = {
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.base = 0x62,
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/*
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* Only 0x62 and 0x66 are required. But, this is not supported by
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* standard IO decodes and there are only 4 generic I/O windows
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* available. Hence, open a window from 0x62-0x67.
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*/
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.size = 5,
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},
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.generic_io_range[1] = {
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.base = 0x800, /* EC_HOST_CMD_REGION0 */
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.size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */
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},
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.generic_io_range[2] = {
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.base = 0x900, /* EC_LPC_ADDR_MEMMAP */
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.size = 255, /* EC_MEMMAP_SIZE */
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},
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.generic_io_range[3] = {
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.base = 0x200, /* EC_LPC_ADDR_HOST_DATA */
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.size = 8, /* 0x200 - 0x207 */
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},
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.io_mode = ESPI_IO_MODE_QUAD,
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.op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
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.crc_check_enable = 1,
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.dedicated_alert_pin = 1,
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.periph_ch_en = 1,
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.vw_ch_en = 1,
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.oob_ch_en = 0,
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.flash_ch_en = 0,
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.vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12),
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}"
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register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
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device domain 0 on
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subsystemid 0x1022 0x1510 inherit
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device pci 0.0 on end # Root Complex
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device pci 0.2 on end # IOMMU
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device pci 1.0 on end # Dummy Host Bridge, must be enabled
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device pci 1.1 off end # GPP Bridge 0
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device pci 1.2 on end # GPP Bridge 1 - Wifi
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device pci 1.3 on end # GPP Bridge 2 - SD
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device pci 1.4 off end # GPP Bridge 3
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device pci 1.5 off end # GPP Bridge 4
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device pci 8.0 on end # Dummy Host Bridge, must be enabled
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device pci 8.1 on # Internal GPP Bridge 0 to Bus A
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device pci 0.0 on end # Internal GPU
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device pci 0.1 on end # Display HDA
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device pci 0.2 on end # Crypto Coprocesor
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device pci 0.5 on end # Audio
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device pci 0.6 on end # HDA
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device pci 0.7 on end # non-Sensor Fusion Hub device
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end
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device pci 8.2 on # Internal GPP Bridge 0 to Bus B
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device pci 0.0 on end # AHCI
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end
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device pci 14.0 on end # SM
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device pci 14.3 on # - D14F3 bridge
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chip ec/google/chromeec
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device pnp 0c09.0 on
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chip ec/google/chromeec/i2c_tunnel
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register "uid" = "1"
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register "remote_bus" = "8"
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device generic 0.0 on
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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register "name" = ""RT58""
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register "uid" = "1"
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register "desc" = ""Realtek RT5682""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(62)"
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register "property_count" = "1"
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on end
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end
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end
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end
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chip ec/google/chromeec/i2c_tunnel
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register "name" = ""MSTH""
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register "uid" = "1"
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register "remote_bus" = "9"
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device generic 1.0 on end
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end
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chip ec/google/chromeec/audio_codec
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register "uid" = "1"
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device generic 0 on end
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end
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end
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end
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end
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device pci 18.0 on end # Data fabric [0-7]
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.4 on end
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device pci 18.5 on end
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device pci 18.6 on end
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end # domain
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chip drivers/generic/max98357a
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register "hid" = ""MX98357A""
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register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)"
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register "sdmode_delay" = "5"
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device generic 0.1 on end
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end
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device mmio 0xfedc5000 on
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chip drivers/i2c/tpm
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register "hid" = ""GOOG0005""
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register "desc" = ""Cr50 TPM""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)"
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device i2c 50 on end
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end
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end
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device mmio 0xfedca000 off end # UART1
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device mmio 0xfedce000 off end # UART2
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device mmio 0xfedcf000 off end # UART3
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end # chip soc/amd/picasso
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