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mb/google/zork: Drop power and reset control in romstage for dalboz 

This change drops power and reset control for non PCIe devices in
romstage for dalboz reference as this is not required.

 +---------------------------------------------------------------------------------------+
 | GPIO|    Net name   | External| Internal| Domain| State at reset | State on S3 resume |
 |  #  |               | Pull    | Pull    |       |                |                    |
 +---------------------------------------------------------------------------------------+
 |  5  | PEN_POWER_EN  | 100K PD |   PD    | S5    | Powered off    | Powered on         |
 |     |               |         |         |       | (because of    | (since power is not|
 |     |               |         |         |       |  internal PD)  |  disabled when     |
 |     |               |         |         |       |                |  entering S3)      |
 +---------------------------------------------------------------------------------------+
 |  6  |EN_PWR_TOUCHPAD| 499K PD |   PU    | S5    | Powered on     | Powered on         |
 |     |               |         |         |       | (because of    | (since trackpad    |
 |     |               |         |         |       |  internal PU)  |  is wake source)   |
 +---------------------------------------------------------------------------------------+
 | 68  | EMMC_RESET_L  | 100K PU |   PD    | S0    |  Asserted      | Asserted           |
 |     |               |         |         |       |  (because of   | (because of        |
 |     |               |         |         |       |   internal PD) |  internal PD)      |
 +---------------------------------------------------------------------------------------+
 | 76  | EN_PWR_CAMERA | 499K PD |   PD    | S0    | Powered off    | Powered off        |
 |     |               |         |         |       | (because of    | (because of        |
 |     |               |         |         |       |  internal PD)  |  internal PD)      |
 +---------------------------------------------------------------------------------------+
 | 140 | USI_RESET     | 10K PD  |   PD    | S0    | Deasserted     | Deasserted         |
 |     |               |         |         |       | (because of    | (because of        |
 |     |               |         |         |       |  internal PD)  |  internal PD)      |
 +---------------------------------------------------------------------------------------+
 | 141 | USB_HUB_RST_L | 10K PU  |   PD    | S0    | Asserted       | Asserted           |
 |     |               |         |         |       | (because of    | (because of        |
 |     |               |         |         |       | internal PD)   |  internal PD)      |
 +---------------------------------------------------------------------------------------+
 +---------------------------------------------------------------------------------------+
 | 67  |EN_PWR_TOUCHPAD| 10K PU  |   PD    | S0    | Powered off    | Powered off        |
 |     |_PS2 (pre-V3)  |         |         |       | (because of    | (because of        |
 |     |               |         |         |       |  internal PD)  |  internal PD)      |
 +---------------------------------------------------------------------------------------+

GPIO_140 starts deasserted out of reset and S3 resume, but gets
asserted in ramstage since it is eventually deasserted by OS using
ACPI methods.

BUG=b:154351731

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ie792a5a9d6420763ff10d1e475c094b6ee514888
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2020-07-14 12:42:08 -07:00 committed by Aaron Durbin
parent 9961343e67
commit ddfec569d1
1 changed files with 0 additions and 24 deletions
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24
src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
View File

@ -10,55 +10,31 @@
#include <variant/gpio.h> #include <variant/gpio.h>
static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = { static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = {
/* PEN_POWER_EN - reset */
PAD_GPO(GPIO_5, LOW),
/* PCIE_RST1_L - Variable timings (May remove) */ /* PCIE_RST1_L - Variable timings (May remove) */
PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
/* NVME_AUX_RESET_L */ /* NVME_AUX_RESET_L */
PAD_GPO(GPIO_40, HIGH), PAD_GPO(GPIO_40, HIGH),
/* EN_PWR_TOUCHPAD_PS2 - reset */
PAD_GPO(GPIO_67, LOW),
/* EMMC_RESET - reset (default stuffing unused)*/
PAD_GPO(GPIO_68, HIGH),
/* EN_PWR_CAMERA - reset */
PAD_GPO(GPIO_76, LOW),
/* CLK_REQ0_L - WIFI */ /* CLK_REQ0_L - WIFI */
PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP), PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP),
/* CLK_REQ1_L - SD Card */ /* CLK_REQ1_L - SD Card */
PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP), PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP),
/* CLK_REQ2_L - NVMe */ /* CLK_REQ2_L - NVMe */
PAD_NF(GPIO_116, CLK_REQ2_L, PULL_UP), PAD_NF(GPIO_116, CLK_REQ2_L, PULL_UP),
/* USI_RESET - reset */
PAD_GPO(GPIO_140, HIGH),
/* USB_HUB_RST_L - reset*/
PAD_GPO(GPIO_141, LOW),
/* SD_AUX_RESET_L */ /* SD_AUX_RESET_L */
PAD_GPO(GPIO_142, HIGH), PAD_GPO(GPIO_142, HIGH),
}; };
static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = { static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = {
/* PEN_POWER_EN - reset */
PAD_GPO(GPIO_5, LOW),
/* EN_PWR_TOUCHPAD_PS2 - reset */
PAD_GPO(GPIO_6, LOW),
/* PCIE_RST1_L - Variable timings (May remove) */ /* PCIE_RST1_L - Variable timings (May remove) */
PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
/* NVME_AUX_RESET_L */ /* NVME_AUX_RESET_L */
PAD_GPO(GPIO_40, HIGH), PAD_GPO(GPIO_40, HIGH),
/* EMMC_RESET - reset (default stuffing unused)*/
PAD_GPO(GPIO_68, HIGH),
/* EN_PWR_CAMERA - reset */
PAD_GPO(GPIO_76, LOW),
/* CLK_REQ0_L - WIFI */ /* CLK_REQ0_L - WIFI */
PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP), PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP),
/* CLK_REQ1_L - SD Card */ /* CLK_REQ1_L - SD Card */
PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP), PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP),
/* CLK_REQ2_L - NVMe */ /* CLK_REQ2_L - NVMe */
PAD_NF(GPIO_116, CLK_REQ2_L, PULL_UP), PAD_NF(GPIO_116, CLK_REQ2_L, PULL_UP),
/* USI_RESET - reset */
PAD_GPO(GPIO_140, HIGH),
/* USB_HUB_RST_L - reset*/
PAD_GPO(GPIO_141, LOW),
/* SD_AUX_RESET_L */ /* SD_AUX_RESET_L */
PAD_GPO(GPIO_142, HIGH), PAD_GPO(GPIO_142, HIGH),
}; };