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intel post-car: Increase stacktop alignment 

Align top of stack to 8 bytes, value documented as FSP1.1 requirement.
Also fix some cases of uintptr_t casted to unsigned long.

Change-Id: I5bbd100eeb673417da205a2c2c3410fef1af61f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17461
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Kyösti Mälkki 2016-11-17 22:39:29 +02:00
parent b17f4e8d26
commit de01136484
5 changed files with 7 additions and 12 deletions
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4
src/cpu/intel/haswell/romstage.c
View File

@ -69,15 +69,13 @@ static inline u32 *stack_push(u32 *stack, u32 value)
* cache-as-ram is torn down as well as the MTRR settings to use. */
static void *setup_romstage_stack_after_car(void)
{
uintptr_t top_of_stack;
int num_mtrrs;
u32 *slot;
u32 mtrr_mask_upper;
u32 top_of_ram;
/* Top of stack needs to be aligned to a 4-byte boundary. */
top_of_stack = romstage_ram_stack_top() & ~3;
slot = (void *)top_of_stack;
slot = (void *)romstage_ram_stack_top();
num_mtrrs = 0;
/* The upper bits of the MTRR mask need to set according to the number

4
src/drivers/intel/fsp1_1/stack.c
View File

@ -35,14 +35,12 @@ void *setup_stack_and_mtrrs(void)
uint32_t max_mtrrs;
uint32_t num_mtrrs;
uint32_t *slot;
unsigned long top_of_stack;
/* Display the MTTRs */
soc_display_mtrrs();
/* Top of stack needs to be aligned to a 8-byte boundary. */
top_of_stack = romstage_ram_stack_top();
slot = (void *)top_of_stack;
slot = (void *)romstage_ram_stack_top();
num_mtrrs = 0;
max_mtrrs = soc_get_variable_mtrr_count(NULL);

3
src/lib/romstage_stack.c
View File

@ -44,5 +44,8 @@ uintptr_t romstage_ram_stack_top(void)
uintptr_t stack_top = romstage_ram_stack_base(ROMSTAGE_RAM_STACK_SIZE,
ROMSTAGE_STACK_CBMEM);
stack_top += ROMSTAGE_RAM_STACK_SIZE;
/* Make it aligned to a 8-byte boundary. */
stack_top = ALIGN_DOWN(stack_top, 8);
return stack_top;
}

4
src/soc/intel/baytrail/romstage/romstage.c
View File

@ -261,15 +261,13 @@ static inline uint32_t *stack_push(u32 *stack, u32 value)
* cache-as-ram is torn down as well as the MTRR settings to use. */
static void *setup_stack_and_mttrs(void)
{
unsigned long top_of_stack;
int num_mtrrs;
uint32_t *slot;
uint32_t mtrr_mask_upper;
uint32_t top_of_ram;
/* Top of stack needs to be aligned to a 4-byte boundary. */
top_of_stack = romstage_ram_stack_top() & ~3;
slot = (void *)top_of_stack;
slot = (void *)romstage_ram_stack_top();
num_mtrrs = 0;
/* The upper bits of the MTRR mask need to set according to the number

4
src/soc/intel/broadwell/romstage/stack.c
View File

@ -34,15 +34,13 @@ static inline uint32_t *stack_push(u32 *stack, u32 value)
* cache-as-ram is torn down as well as the MTRR settings to use. */
void *setup_stack_and_mttrs(void)
{
unsigned long top_of_stack;
int num_mtrrs;
uint32_t *slot;
uint32_t mtrr_mask_upper;
uint32_t top_of_ram;
/* Top of stack needs to be aligned to a 4-byte boundary. */
top_of_stack = romstage_ram_stack_top() & ~3;
slot = (void *)top_of_stack;
slot = (void *)romstage_ram_stack_top();
num_mtrrs = 0;
/* The upper bits of the MTRR mask need to set according to the number