soc/amd: factor out common noncar bootblock

This code is identical for all non-CAR AMD SoCs, so factor it out to
soc/amd/common/block/cpu/noncar/bootblock.c to avoid code duplication.
Also integrate the bootblock.c improvement to include cpu/cpu.h which
provides cpuid_eax from commit 68eb439d80 ("soc/amd/picasso: Clean up
includes").

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I42e4aa85efd6312a3ab37f0323a35f6dd7acd8e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This commit is contained in:
Felix Held 2022-10-14 22:59:40 +02:00
parent f73a3a5e08
commit de10d5bf4d
9 changed files with 2 additions and 159 deletions

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@ -8,7 +8,6 @@ subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage
all-y += config.c
all-y += aoac.c
bootblock-y += bootblock.c
bootblock-y += early_fch.c
bootblock-y += espi_util.c
bootblock-y += gpio.c

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@ -1,5 +1,6 @@
ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR),y)
bootblock-y += bootblock.c
bootblock-y += early_cache.c
bootblock-y += pre_c.S
bootblock-y += write_resume_eip.c

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@ -4,6 +4,7 @@
#include <amdblocks/cpu.h>
#include <bootblock_common.h>
#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/x86/tsc.h>
#include <soc/southbridge.h>
#include <soc/psp_transfer.h>

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@ -10,7 +10,6 @@ subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage
all-y += config.c
all-y += aoac.c
bootblock-y += bootblock.c
bootblock-y += early_fch.c
bootblock-y += espi_util.c
bootblock-y += gpio.c

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@ -1,52 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* TODO: Check if this is still correct */
#include <amdblocks/amd_pci_mmconf.h>
#include <amdblocks/cpu.h>
#include <bootblock_common.h>
#include <console/console.h>
#include <cpu/x86/tsc.h>
#include <soc/southbridge.h>
#include <soc/psp_transfer.h>
#include <stdint.h>
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
early_cache_setup();
write_resume_eip();
enable_pci_mmconf();
/*
* base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz
* to get micro-seconds granularity.
*/
base_timestamp /= tsc_freq_mhz();
if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
boot_with_psp_timestamp(base_timestamp);
/*
* if VBOOT_STARTS_BEFORE_BOOTBLOCK is not selected or
* previous step did nothing, proceed with normal bootblock main.
*/
bootblock_main_with_basetime(base_timestamp);
}
void bootblock_soc_early_init(void)
{
fch_pre_init();
}
void bootblock_soc_init(void)
{
u32 val = cpuid_eax(1);
printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) {
verify_psp_transfer_buf();
show_psp_transfer_info();
}
fch_early_init();
}

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@ -11,7 +11,6 @@ subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage
all-y += config.c
all-y += aoac.c
bootblock-y += bootblock.c
bootblock-y += early_fch.c
bootblock-y += espi_util.c
bootblock-y += gpio.c

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@ -1,52 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* TODO: Update for Morgana */
#include <amdblocks/amd_pci_mmconf.h>
#include <amdblocks/cpu.h>
#include <bootblock_common.h>
#include <console/console.h>
#include <cpu/x86/tsc.h>
#include <soc/southbridge.h>
#include <soc/psp_transfer.h>
#include <stdint.h>
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
early_cache_setup();
write_resume_eip();
enable_pci_mmconf();
/*
* base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz
* to get micro-seconds granularity.
*/
base_timestamp /= tsc_freq_mhz();
if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
boot_with_psp_timestamp(base_timestamp);
/*
* if VBOOT_STARTS_BEFORE_BOOTBLOCK is not selected or
* previous step did nothing, proceed with normal bootblock main.
*/
bootblock_main_with_basetime(base_timestamp);
}
void bootblock_soc_early_init(void)
{
fch_pre_init();
}
void bootblock_soc_init(void)
{
u32 val = cpuid_eax(1);
printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) {
verify_psp_transfer_buf();
show_psp_transfer_info();
}
fch_early_init();
}

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@ -9,7 +9,6 @@ subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../common/psp_verstage
all-y += config.c
all-y += aoac.c
bootblock-y += bootblock.c
bootblock-y += early_fch.c
bootblock-y += gpio.c
bootblock-y += i2c.c

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@ -1,51 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/amd_pci_mmconf.h>
#include <amdblocks/cpu.h>
#include <bootblock_common.h>
#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/x86/tsc.h>
#include <soc/psp_transfer.h>
#include <soc/southbridge.h>
#include <stdint.h>
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
early_cache_setup();
write_resume_eip();
enable_pci_mmconf();
/*
* base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz
* when we use micro-seconds granularity for Zork
*/
base_timestamp /= tsc_freq_mhz();
if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
boot_with_psp_timestamp(base_timestamp);
/*
* if VBOOT_STARTS_BEFORE_BOOTBLOCK is not selected or
* previous step did nothing, proceed with normal bootblock main.
*/
bootblock_main_with_basetime(base_timestamp);
}
void bootblock_soc_early_init(void)
{
fch_pre_init();
}
void bootblock_soc_init(void)
{
u32 val = cpuid_eax(1);
printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) {
verify_psp_transfer_buf();
show_psp_transfer_info();
}
fch_early_init();
}