x4x/gma.c: Add VESA native resolution mode
This patch implements native resolution, VESA mode, on the VGA output of x4x. It relies on EDID to modeset, but has a fallback-mode (640 x 480 @ 60Hz) if this is no EDID could be found. This fallback mode only works in textmode since in VESA mode some payloads (grub2) rely on VBE info, which is being generated from an EDID. Change-Id: I247ea7171ba3c5dc3b209d00e4dcb2d2069abd75 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16498 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Arthur Heymans
Martin Roth
parent
eff596b51a
commit
de14ea77c3
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@ -26,24 +26,68 @@
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <kconfig.h>
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#include <commonlib/helpers.h>
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#include "drivers/intel/gma/i915_reg.h"
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#include "chip.h"
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#include "x4x.h"
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#include <drivers/intel/gma/intel_bios.h>
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#include <drivers/intel/gma/edid.h>
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#include <drivers/intel/gma/i915.h>
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#include <pc80/vga.h>
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#include <pc80/vga_io.h>
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#define BASE_FREQUENCY 96000
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static u8 edid_is_present(u8 *edid, u32 edid_size)
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{
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u32 i;
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for (i = 0; i < edid_size; i++) {
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if (*(edid + i) != 0)
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return 1;
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}
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return 0;
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}
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static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
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u8 *mmio)
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u8 *mmio, u32 physbase, u16 piobase, u32 lfb)
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{
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int i;
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u32 hactive, vactive;
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u8 edid_data[128];
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struct edid edid;
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struct edid_mode *mode;
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u8 edid_is_found;
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/* Initialise mode variables for 640 x 480 @ 60Hz */
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u32 hactive = 640, vactive = 480;
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u32 right_border = 0, bottom_border = 0;
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int hpolarity = 0, vpolarity = 0;
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u32 hsync = 96, vsync = 2;
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u32 hblank = 160, vblank = 45;
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u32 hfront_porch = 16, vfront_porch = 10;
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u32 target_frequency = 25175;
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u32 err_most = 0xffffffff;
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u32 pixel_p1 = 1;
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u32 pixel_n = 1;
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u32 pixel_m1 = 1;
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u32 pixel_m2 = 1;
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u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000;
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u32 data_m1;
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u32 data_n1 = 0x00800000;
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u32 link_m1;
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u32 link_n1 = 0x00040000;
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vga_gr_write(0x18, 0);
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/* Set up GTT */
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for (i = 0; i < 0x1000; i++) {
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outl((i << 2) | 1, piobase);
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outl(physbase + (i << 12) + 1, piobase + 4);
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}
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write32(mmio + VGA0, 0x31108);
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write32(mmio + VGA1, 0x31406);
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@ -73,88 +117,225 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
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for (i = 0; i <= 0x18; i++)
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vga_cr_write(i, cr[i]);
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udelay(1);
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intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128);
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intel_gmbus_stop(mmio + GMBUS0);
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decode_edid(edid_data,
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sizeof(edid_data), &edid);
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mode = &edid.mode;
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/* Disable screen memory to prevent garbage from appearing. */
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vga_sr_write(1, vga_sr_read(1) | 0x20);
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hactive = 640;
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vactive = 400;
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edid_is_found = edid_is_present(edid_data, sizeof(edid_data));
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if (edid_is_found) {
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printk(BIOS_DEBUG, "EDID is not null");
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hactive = edid.x_resolution;
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vactive = edid.y_resolution;
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right_border = mode->hborder;
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bottom_border = mode->vborder;
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hpolarity = (mode->phsync == '-');
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vpolarity = (mode->pvsync == '-');
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vsync = mode->vspw;
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hsync = mode->hspw;
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vblank = mode->vbl;
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hblank = mode->hbl;
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hfront_porch = mode->hso;
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vfront_porch = mode->vso;
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target_frequency = mode->pixel_clock;
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} else
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printk(BIOS_DEBUG, "EDID is null, using 640 x 480 @ 60Hz mode");
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if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
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vga_sr_write(1, 1);
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vga_sr_write(0x2, 0xf);
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vga_sr_write(0x3, 0x0);
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vga_sr_write(0x4, 0xe);
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vga_gr_write(0, 0x0);
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vga_gr_write(1, 0x0);
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vga_gr_write(2, 0x0);
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vga_gr_write(3, 0x0);
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vga_gr_write(4, 0x0);
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vga_gr_write(5, 0x0);
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vga_gr_write(6, 0x5);
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vga_gr_write(7, 0xf);
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vga_gr_write(0x10, 0x1);
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vga_gr_write(0x11, 0);
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edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
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write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
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| DISPPLANE_BGRX888);
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write32(mmio + DSPADDR(0), 0);
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write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
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write32(mmio + DSPSURF(0), 0);
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for (i = 0; i < 0x100; i++)
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write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
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} else {
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vga_textmode_init();
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}
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u32 candn, candm1, candm2, candp1;
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for (candn = 1; candn <= 4; candn++) {
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for (candm1 = 23; candm1 >= 16; candm1--) {
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for (candm2 = 11; candm2 >= 5; candm2--) {
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for (candp1 = 8; candp1 >= 1; candp1--) {
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u32 m = 5 * (candm1 + 2) + (candm2 + 2);
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u32 p = candp1 * 10; /* 10 == p2 */
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u32 vco = DIV_ROUND_CLOSEST(
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BASE_FREQUENCY * m, candn + 2);
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u32 dot = DIV_ROUND_CLOSEST(vco, p);
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u32 this_err = ABS(dot - target_frequency);
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if (this_err < err_most) {
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err_most = this_err;
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pixel_n = candn;
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pixel_m1 = candm1;
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pixel_m2 = candm2;
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pixel_p1 = candp1;
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}
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}
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}
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}
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}
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if (err_most == 0xffffffff) {
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printk(BIOS_ERR, "Couldn't find GFX clock divisors\n");
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return;
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}
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link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency;
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data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock)
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/ (link_frequency * 8 * 4);
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printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
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hactive, vactive);
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printk(BIOS_DEBUG, "Borders %d x %d\n",
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right_border, bottom_border);
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printk(BIOS_DEBUG, "Blank %d x %d\n",
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hblank, vblank);
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printk(BIOS_DEBUG, "Sync %d x %d\n",
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hsync, vsync);
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printk(BIOS_DEBUG, "Front porch %d x %d\n",
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hfront_porch, vfront_porch);
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printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock
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? "Spread spectrum clock\n" : "DREF clock\n"));
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printk(BIOS_DEBUG, "Polarities %d, %d\n",
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hpolarity, vpolarity);
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printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
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data_m1, data_n1);
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printk(BIOS_DEBUG, "Link frequency %d kHz\n",
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link_frequency);
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printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n",
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link_m1, link_n1);
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printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",
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pixel_n, pixel_m1, pixel_m2, pixel_p1);
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printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
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BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) /
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(pixel_n + 2) / (pixel_p1 * 10));
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mdelay(1);
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write32(mmio + FP0(0), 0x31108);
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write32(mmio + DPLL(0),
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DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
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| DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
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| 0x10601
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);
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write32(mmio + FP0(0), (pixel_n << 16)
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| (pixel_m1 << 8) | pixel_m2);
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write32(mmio + DPLL(0), DPLL_VCO_ENABLE
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| DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL
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| (0x10000 << (pixel_p1 - 1))
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| (6 << 9));
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mdelay(1);
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write32(mmio + DPLL(0),
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DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
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| DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
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| 0x10601
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);
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write32(mmio + DPLL(0), DPLL_VCO_ENABLE
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| DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL
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| (0x10000 << (pixel_p1 - 1))
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| (6 << 9));
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write32(mmio + ADPA, ADPA_DAC_ENABLE
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| ADPA_PIPE_A_SELECT
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| ADPA_CRT_HOTPLUG_MONITOR_COLOR
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| ADPA_CRT_HOTPLUG_ENABLE
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| ADPA_USE_VGA_HVPOLARITY
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| ADPA_VSYNC_CNTL_ENABLE
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| ADPA_HSYNC_CNTL_ENABLE
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| ADPA_DPMS_ON
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);
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| (vpolarity ? ADPA_VSYNC_ACTIVE_LOW :
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ADPA_VSYNC_ACTIVE_HIGH)
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| (hpolarity ? ADPA_HSYNC_ACTIVE_LOW :
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ADPA_HSYNC_ACTIVE_HIGH));
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write32(mmio + HTOTAL(0),
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((hactive - 1) << 16)
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((hactive + right_border + hblank - 1) << 16)
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| (hactive - 1));
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write32(mmio + HBLANK(0),
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((hactive - 1) << 16)
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| (hactive - 1));
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((hactive + right_border + hblank - 1) << 16)
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| (hactive + right_border - 1));
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write32(mmio + HSYNC(0),
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((hactive - 1) << 16)
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| (hactive - 1));
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((hactive + right_border + hfront_porch + hsync - 1) << 16)
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| (hactive + right_border + hfront_porch - 1));
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write32(mmio + VTOTAL(0), ((vactive - 1) << 16)
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| (vactive - 1));
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write32(mmio + VBLANK(0), ((vactive - 1) << 16)
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write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)
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| (vactive - 1));
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write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
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| (vactive + bottom_border - 1));
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write32(mmio + VSYNC(0),
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((vactive - 1) << 16)
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| (vactive - 1));
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((vactive + bottom_border + vfront_porch + vsync - 1) << 16)
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| (vactive + bottom_border + vfront_porch - 1));
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write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
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write32(mmio + PF_WIN_POS(0), 0);
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if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
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write32(mmio + PIPESRC(0), ((hactive - 1) << 16)
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| (vactive - 1));
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write32(mmio + PF_CTL(0), 0);
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write32(mmio + PF_WIN_SZ(0), 0);
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write32(mmio + PFIT_CONTROL, 0);
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} else {
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write32(mmio + PIPESRC(0), (639 << 16) | 399);
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write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
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write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3);
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write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
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write32(mmio + PFIT_CONTROL, 0xa0000000);
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write32(mmio + PFIT_CONTROL, 0x80000000);
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}
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mdelay(1);
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write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);
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write32(mmio + PIPE_DATA_N1(0), data_n1);
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write32(mmio + PIPE_LINK_M1(0), link_m1);
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write32(mmio + PIPE_LINK_N1(0), link_n1);
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write32(mmio + 0x000f000c, 0x00002040);
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mdelay(1);
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write32(mmio + 0x000f000c, 0x00002050);
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write32(mmio + 0x00060100, 0x00044000);
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mdelay(1);
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write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
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write32(mmio + 0x000f0008, 0x00000040);
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write32(mmio + 0x000f000c, 0x00022050);
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write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
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write32(mmio + PIPECONF(0), PIPECONF_ENABLE
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| PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
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write32(mmio + VGACNTRL, 0x0);
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write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
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if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
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write32(mmio + VGACNTRL, VGA_DISP_DISABLE);
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write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
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| DISPPLANE_BGRX888);
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mdelay(1);
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} else {
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write32(mmio + VGACNTRL, 0xc4008e);
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}
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write32(mmio + ADPA, ADPA_DAC_ENABLE
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| ADPA_PIPE_A_SELECT
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| ADPA_CRT_HOTPLUG_MONITOR_COLOR
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| ADPA_CRT_HOTPLUG_ENABLE
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| ADPA_USE_VGA_HVPOLARITY
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| ADPA_VSYNC_CNTL_ENABLE
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| ADPA_HSYNC_CNTL_ENABLE
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| ADPA_DPMS_ON
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);
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| (vpolarity ? ADPA_VSYNC_ACTIVE_LOW :
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ADPA_VSYNC_ACTIVE_HIGH)
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| (hpolarity ? ADPA_HSYNC_ACTIVE_LOW :
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ADPA_HSYNC_ACTIVE_HIGH));
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vga_textmode_init();
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write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
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/* Enable screen memory. */
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vga_sr_write(1, vga_sr_read(1) & ~0x20);
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@ -162,18 +343,32 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
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/* Clear interrupts. */
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write32(mmio + DEIIR, 0xffffffff);
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write32(mmio + SDEIIR, 0xffffffff);
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if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
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memset((void *) lfb, 0,
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hactive * vactive * 4);
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set_vbe_mode_info_valid(&edid, lfb);
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}
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}
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static void native_init(struct device *dev)
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{
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struct resource *lfb_res;
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struct resource *pio_res;
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u32 physbase;
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struct resource *gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
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struct northbridge_intel_x4x_config *conf = dev->chip_info;
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lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2);
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pio_res = find_resource(dev, PCI_BASE_ADDRESS_4);
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physbase = pci_read_config32(dev, 0x5c) & ~0xf;
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if (gtt_res && gtt_res->base) {
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printk(BIOS_SPEW,
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"Initializing VGA without OPROM. MMIO 0x%llx\n",
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gtt_res->base);
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intel_gma_init(conf, res2mmio(gtt_res, 0, 0));
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intel_gma_init(conf, res2mmio(gtt_res, 0, 0),
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physbase, pio_res->base, lfb_res->base);
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}
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/* Linux relies on VBT for panel info. */
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@ -182,6 +377,7 @@ static void native_init(struct device *dev)
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static void gma_func0_init(struct device *dev)
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{
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u16 reg16;
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u32 reg32;
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/* IGD needs to be Bus Master */
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@ -189,6 +385,12 @@ static void gma_func0_init(struct device *dev)
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reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
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pci_write_config32(dev, PCI_COMMAND, reg32);
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/* configure GMBUSFREQ */
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reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x2,0)), 0xcc);
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reg16 &= ~0x1ff;
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reg16 |= 0xbc;
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pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x2,0)), 0xcc, reg16);
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if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
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native_init(dev);
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else
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