soc/ucb/riscv: Add chip_operations stub

Change-Id: Ie4f70429c516fff613d372fec7c1c955645f1c6d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>

src/soc/ucb/riscv/Makefile.inc

@@ -4,4 +4,6 @@ romstage-y += cbmem.c
 
 ramstage-y += cbmem.c
 
+ramstage-y += chip.c
+
 endif

src/soc/ucb/riscv/chip.c

@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+
+struct chip_operations soc_ucb_riscv_ops = {
+	CHIP_NAME("UCB RISC-V")
+};