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soc/intel/common: Move L1_substates_control to pcie_rp.h 

L1_substates_control is common define. Move out of soc level.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I54574b606985e82d00beb1a61cce3097580366a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Eric Lai 2021-01-11 16:14:14 +08:00 committed by Patrick Georgi
parent cb18524b4a
commit de2ab41fc4
5 changed files with 16 additions and 24 deletions
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8
src/soc/intel/alderlake/chip.h
View File

@ -7,6 +7,7 @@
#include <intelblocks/cfg.h>
#include <intelblocks/gpio.h>
#include <intelblocks/gspi.h>
#include <intelblocks/pcie_rp.h>
#include <soc/gpe.h>
#include <soc/pch.h>
#include <soc/pci_devs.h>
@ -136,12 +137,7 @@ struct soc_intel_alderlake_config {
uint8_t PcieRpClkReqDetect[CONFIG_MAX_PCH_ROOT_PORTS];
/* PCIe RP L1 substate */
enum L1_substates_control {
L1_SS_FSP_DEFAULT,
L1_SS_DISABLED,
L1_SS_L1_1,
L1_SS_L1_2,
} PcieRpL1Substates[CONFIG_MAX_PCH_ROOT_PORTS];
enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_PCH_ROOT_PORTS];
/* PCIe LTR: Enable (1) / Disable (0) */
uint8_t PcieRpLtrEnable[CONFIG_MAX_PCH_ROOT_PORTS];

8
src/soc/intel/common/block/include/intelblocks/pcie_rp.h
View File

@ -63,4 +63,12 @@ void pcie_rp_update_devicetree(const struct pcie_rp_group *groups);
*/
uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups);
/* This enum is for passing into an FSP UPD, typically PcieRpL1Substates */
enum L1_substates_control {
L1_SS_FSP_DEFAULT,
L1_SS_DISABLED,
L1_SS_L1_1,
L1_SS_L1_2,
};
#endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */

8
src/soc/intel/elkhartlake/chip.h
View File

@ -7,6 +7,7 @@
#include <intelblocks/cfg.h>
#include <intelblocks/gpio.h>
#include <intelblocks/gspi.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/power_limit.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
@ -116,12 +117,7 @@ struct soc_intel_elkhartlake_config {
uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
/* PCIe RP L1 substate */
enum L1_substates_control {
L1_SS_FSP_DEFAULT,
L1_SS_DISABLED,
L1_SS_L1_1,
L1_SS_L1_2,
} PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
/* SMBus */
uint8_t SmbusEnable;

8
src/soc/intel/jasperlake/chip.h
View File

@ -7,6 +7,7 @@
#include <intelblocks/cfg.h>
#include <intelblocks/gpio.h>
#include <intelblocks/gspi.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/power_limit.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
@ -114,12 +115,7 @@ struct soc_intel_jasperlake_config {
uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
/* PCIe RP L1 substate */
enum L1_substates_control {
L1_SS_FSP_DEFAULT,
L1_SS_DISABLED,
L1_SS_L1_1,
L1_SS_L1_2,
} PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
/* SMBus */
uint8_t SmbusEnable;

8
src/soc/intel/tigerlake/chip.h
View File

@ -7,6 +7,7 @@
#include <intelblocks/cfg.h>
#include <intelblocks/gpio.h>
#include <intelblocks/gspi.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/power_limit.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
@ -247,12 +248,7 @@ struct soc_intel_tigerlake_config {
uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS];
/* PCIe RP L1 substate */
enum L1_substates_control {
L1_SS_FSP_DEFAULT,
L1_SS_DISABLED,
L1_SS_L1_1,
L1_SS_L1_2,
} PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
/* PCIe LTR: Enable (1) / Disable (0) */
uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];