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mb/google/poppy/variants/nocturne: disable p-states 

Set register speed_shift_enable=0 in devicetree to disable
p-states in coreboot as a temporary workaround for an SoC hang.

BUG=b:79666828
BRANCH=none
TEST="emerge-nocturne depthcharge coreboot chromeos-bootimage",
flash spi image onto nocturne, boot to kernel and verify device
stays alive and responsive for several minutes without locking up.

Change-Id: I71ed4c80c109b28ffa85d48338ce3a62396d272e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Nick Vaccaro 2018-06-18 21:56:25 -07:00 committed by Patrick Georgi
parent 97bdb9aa31
commit de31587a3a
1 changed files with 2 additions and 1 deletions
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3
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
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@ -60,7 +60,8 @@ chip soc/intel/skylake
register "PmTimerDisabled" = "1" register "PmTimerDisabled" = "1"
register "VmxEnable" = "1" register "VmxEnable" = "1"
register "speed_shift_enable" = "1" # Disable P-States
register "speed_shift_enable" = "0"
register "dptf_enable" = "1" register "dptf_enable" = "1"
register "tdp_pl2_override" = "15" register "tdp_pl2_override" = "15"
register "psys_pmax" = "45" register "psys_pmax" = "45"