This is a general cleanup patch
- drop include/part and move files to include/ - get rid lots of warnings - make resource allocator happy with w83627thg - trivial cbmem resume fix - fix payload and log level settings in abuild - fix kontron mptable for virtual wire mode - drop some dead includes and dead code. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
d650e9934f
commit
de3206a7be
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@ -487,7 +487,7 @@ void suspend_resume(void)
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/* this is to be filled by SB code - startup value what was found */
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u8 acpi_slp_type = 0;
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int acpi_is_wakeup(void)
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static int acpi_is_wakeup(void)
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{
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return (acpi_slp_type == 3);
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}
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@ -600,7 +600,7 @@ void acpi_jump_to_wakeup(void *vector)
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memcpy(lowmem_backup_ptr, lowmem_backup, lowmem_backup_size);
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/* copy wakeup trampoline in place */
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memcpy(WAKEUP_BASE, &__wakeup, &__wakeup_size);
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memcpy((void *)WAKEUP_BASE, &__wakeup, (size_t)&__wakeup_size);
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acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
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}
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@ -24,7 +24,7 @@
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#include <ip_checksum.h>
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#include <boot/tables.h>
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#include <boot/coreboot_tables.h>
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#include "coreboot_table.h"
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#include <arch/coreboot_tables.h>
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#include <string.h>
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#include <version.h>
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#include <device/device.h>
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@ -3,7 +3,11 @@
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#include <string.h>
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#include <device/pci.h>
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#if (CONFIG_DEBUG==1 && CONFIG_GENERATE_PIRQ_TABLE==1)
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#ifndef CONFIG_IRQ_SLOT_COUNT
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#warning "CONFIG_IRQ_SLOT_COUNT is not defined. PIRQ won't work correctly."
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#endif
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#if CONFIG_DEBUG
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static void check_pirq_routing_table(struct irq_routing_table *rt)
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{
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uint8_t *addr = (uint8_t *)rt;
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@ -12,7 +16,6 @@ static void check_pirq_routing_table(struct irq_routing_table *rt)
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printk_info("Checking Interrupt Routing Table consistency...\n");
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#if defined(CONFIG_IRQ_SLOT_COUNT)
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if (sizeof(struct irq_routing_table) != rt->size) {
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printk_warning("Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n",
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sizeof(struct irq_routing_table),
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@ -20,7 +23,6 @@ static void check_pirq_routing_table(struct irq_routing_table *rt)
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);
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rt->size=sizeof(struct irq_routing_table);
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}
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#endif
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for (i = 0; i < rt->size; i++)
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sum += addr[i];
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@ -79,11 +81,8 @@ static int verify_copy_pirq_routing_table(unsigned long addr)
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return 0;
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}
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#else
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#define verify_copy_pirq_routing_table(addr)
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#endif
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#if CONFIG_GENERATE_PIRQ_TABLE==1
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unsigned long copy_pirq_routing_table(unsigned long addr)
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{
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/* Align the table to be 16 byte aligned. */
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@ -98,9 +97,8 @@ unsigned long copy_pirq_routing_table(unsigned long addr)
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pirq_routing_irqs(addr);
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return addr + intel_irq_routing_table.size;
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}
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#endif
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#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_GENERATE_PIRQ_TABLE==1)
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#if CONFIG_PIRQ_ROUTE
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void pirq_routing_irqs(unsigned long addr)
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{
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int i, j, k, num_entries;
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@ -23,12 +23,12 @@
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#include <cpu/cpu.h>
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#include <boot/tables.h>
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#include <boot/coreboot_tables.h>
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#include <arch/coreboot_tables.h>
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#include <arch/pirq_routing.h>
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#include <arch/smp/mpspec.h>
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#include <arch/acpi.h>
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#include <string.h>
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#include <cpu/x86/multiboot.h>
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#include "coreboot_table.h"
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#include <cbmem.h>
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#include <lib.h>
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@ -167,7 +167,7 @@ struct lb_memory *write_tables(void)
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acpi_write_rsdp(low_rsdp,
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(acpi_rsdt_t *)(high_rsdp->rsdt_address),
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(acpi_xsdt_t *)(high_rsdp->xsdt_address));
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(acpi_xsdt_t *)((unsigned long)high_rsdp->xsdt_address));
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} else {
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printk_err("ERROR: Didn't find RSDP in high table.\n");
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}
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@ -355,7 +355,7 @@ typedef struct acpi_ecdt {
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} __attribute__ ((packed)) acpi_ecdt_t;
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/* These are implemented by the target port */
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/* These are implemented by the target port or north/southbridge*/
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unsigned long write_acpi_tables(unsigned long addr);
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unsigned long acpi_fill_madt(unsigned long current);
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unsigned long acpi_fill_mcfg(unsigned long current);
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@ -414,7 +414,10 @@ int acpi_get_sleep_type(void);
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#endif
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/* northbridge/amd/amdfam10/amdfam10_acpi.c */
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unsigned long acpi_add_ssdt_pstates(acpi_rsdp_t *rsdp, unsigned long current);
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/* cpu/intel/speedstep/acpi.c */
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void generate_cpu_entries(void);
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#define ACPI_WRITE_MADT_IOAPIC(dev,id) \
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do { \
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@ -20,5 +20,6 @@ extern struct cmos_option_table option_table;
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/* defined by mainboard.c if the mainboard requires extra resources */
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int add_mainboard_resources(struct lb_memory *mem);
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int add_northbridge_resources(struct lb_memory *mem);
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#endif /* COREBOOT_TABLE_H */
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@ -31,6 +31,8 @@ struct intel_mp_floating
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unsigned char mpf_checksum; /* Checksum (makes sum 0) */
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unsigned char mpf_feature1; /* Standard or configuration ? */
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unsigned char mpf_feature2; /* Bit7 set for IMCR|PIC */
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#define MP_FEATURE_VIRTUALWIRE (1 << 7)
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#define MP_FEATURE_PIC (0 << 7)
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unsigned char mpf_feature3; /* Unused (0) */
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unsigned char mpf_feature4; /* Unused (0) */
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unsigned char mpf_feature5; /* Unused (0) */
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@ -1,6 +1,4 @@
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extern int do_printk(int msg_level, const char *fmt, ...);
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#define printk_emerg(fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg)
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#define printk_alert(fmt, arg...) do_printk(BIOS_ALERT ,fmt, ##arg)
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#define printk_crit(fmt, arg...) do_printk(BIOS_CRIT ,fmt, ##arg)
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@ -224,7 +224,7 @@ void cpu_initialize(void)
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info = cpu_info();
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printk_notice("Initializing CPU #%ld\n", info->index);
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printk_info("Initializing CPU #%ld\n", info->index);
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cpu = info->cpu;
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if (!cpu) {
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@ -31,8 +31,7 @@ it with the version available from LANL.
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#include <device/pci.h>
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#include <delay.h>
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#include <stdlib.h>
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#include <part/hard_reset.h>
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#include <part/init_timer.h>
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#include <reset.h>
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#include <boot/tables.h>
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#include <boot/elf.h>
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#include <cbfs.h>
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@ -19,7 +19,7 @@
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*/
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#include <console/console.h>
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#include <part/fallback_boot.h>
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#include <fallback.h>
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#include <boot/elf.h>
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#include <boot/elf_boot.h>
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#include <boot/coreboot_tables.h>
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@ -54,8 +54,7 @@ void stage1_main(unsigned long bist)
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real_main(bist);
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/* No servicable parts below this line .. */
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#if CAR_DEBUG
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#ifdef CAR_DEBUG
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/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
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unsigned v_esp;
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__asm__ volatile (
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@ -55,7 +55,7 @@ void stage1_main(unsigned long bist)
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/* No servicable parts below this line .. */
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#if CAR_DEBUG
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#ifdef CAR_DEBUG
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/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
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unsigned v_esp;
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__asm__ volatile (
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@ -1,8 +1,27 @@
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/* Copyright (C) 2009 coresystems GmbH
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(Written by Patrick Georgi <patrick.georgi@coresystems.de> for coresystems GmbH
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*/
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009-2010 coresystems GmbH
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* Written by Patrick Georgi <patrick.georgi@coresystems.de>
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* for coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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void cbfs_and_run_core(char*, unsigned ebp);
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void cbfs_and_run_core(const char *, unsigned ebp);
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static void copy_and_run(unsigned cpu_reset)
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{
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@ -34,8 +34,6 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/hypertransport.h>
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#include <part/hard_reset.h>
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#include <part/fallback_boot.h>
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/* The hypertransport link is already optimized in pre-ram code
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* so don't do it again
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@ -32,8 +32,6 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <part/hard_reset.h>
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#include <part/fallback_boot.h>
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#include <delay.h>
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#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
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#include <device/hypertransport.h>
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@ -240,7 +240,25 @@ static void get_resources(device_t dev, struct pnp_info *info)
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resource = new_resource(dev, PNP_IDX_DRQ1);
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resource->size = 1;
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resource->flags |= IORESOURCE_DRQ;
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}
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}
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/* These are not IRQs, but set the flag to have the
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* resource allocator do the right thing
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*/
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if (info->flags & PNP_EN) {
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resource = new_resource(dev, PNP_IDX_EN);
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resource->size = 1;
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resource->flags |= IORESOURCE_IRQ;
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}
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if (info->flags & PNP_MSC0) {
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resource = new_resource(dev, PNP_IDX_MSC0);
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resource->size = 1;
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resource->flags |= IORESOURCE_IRQ;
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}
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if (info->flags & PNP_MSC1) {
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resource = new_resource(dev, PNP_IDX_MSC1);
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resource->size = 1;
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resource->flags |= IORESOURCE_IRQ;
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}
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}
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void pnp_enable_devices(device_t base_dev, struct device_operations *ops,
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@ -25,7 +25,7 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <part/hard_reset.h>
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#include <reset.h>
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/**
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* Read the resources for the root device,
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@ -5,7 +5,7 @@
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <cpu/x86/msr.h>
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#include <part/hard_reset.h>
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#include <reset.h>
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#include <delay.h>
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#include "chip.h"
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@ -4,7 +4,6 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <part/hard_reset.h>
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#include <cpu/x86/msr.h>
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#include "chip.h"
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@ -4,7 +4,6 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <part/hard_reset.h>
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#include <cpu/x86/msr.h>
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#include "chip.h"
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@ -17,6 +17,8 @@ void secondary_cpu_init(void);
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#if CONFIG_HAVE_SMI_HANDLER
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void smm_init(void);
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void smm_lock(void);
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void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
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#endif
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#define __cpu_driver __attribute__ ((used,__section__(".rodata.cpu_driver")))
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@ -1,7 +1,7 @@
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#ifndef CPU_X86_BIST_H
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#define CPU_X86_BIST_H
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static void report_bist_failure(unsigned long bist)
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static void report_bist_failure(u32 bist)
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{
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if (bist != 0) {
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#if CONFIG_USE_PRINTK_IN_CAR
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@ -60,12 +60,13 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void)
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*/
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static inline __attribute__((always_inline)) void stop_this_cpu(void)
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{
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/* Called by an AP when it is ready to halt and wait for a new task */
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for(;;) {
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hlt();
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}
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}
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#else
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void stop_this_cpu(void);
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#endif
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#if ! defined (__ROMCC__) && !defined(__PRE_RAM__)
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@ -24,9 +24,6 @@ static inline unsigned long long rdtscll(void)
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asm volatile ("rdtsc" : "=A" (val));
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return val;
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}
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void init_timer(void);
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#endif
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#endif /* CPU_X86_TSC_H */
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@ -1,7 +1,14 @@
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#ifndef DELAY_H
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#define DELAY_H
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#if !defined( __ROMCC__)
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#if CONFIG_HAVE_INIT_TIMER == 1
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void init_timer(void);
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#else
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#define init_timer() do{} while(0)
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#endif
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void udelay(unsigned usecs);
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void mdelay(unsigned msecs);
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void delay(unsigned secs);
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|
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@ -33,14 +33,17 @@ struct pnp_info {
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struct device_operations *ops;
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unsigned function;
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unsigned flags;
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#define PNP_IO0 0x01
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#define PNP_IO1 0x02
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#define PNP_IO2 0x04
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#define PNP_IO3 0x08
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#define PNP_IRQ0 0x10
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#define PNP_IRQ1 0x20
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#define PNP_DRQ0 0x40
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#define PNP_DRQ1 0x80
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#define PNP_IO0 0x001
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#define PNP_IO1 0x002
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#define PNP_IO2 0x004
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#define PNP_IO3 0x008
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#define PNP_IRQ0 0x010
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#define PNP_IRQ1 0x020
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#define PNP_DRQ0 0x040
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#define PNP_DRQ1 0x080
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#define PNP_EN 0x100
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#define PNP_MSC0 0x200
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#define PNP_MSC1 0x400
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struct io_info io0, io1, io2, io3;
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};
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struct resource *pnp_get_resource(device_t dev, unsigned index);
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|
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@ -1,6 +1,7 @@
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#ifndef DEVICE_PNP_DEF_H
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#define DEVICE_PNP_DEF_H
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#define PNP_IDX_EN 0x30
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#define PNP_IDX_IO0 0x60
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#define PNP_IDX_IO1 0x62
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#define PNP_IDX_IO2 0x64
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@ -9,6 +10,7 @@
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#define PNP_IDX_IRQ1 0x72
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#define PNP_IDX_DRQ0 0x74
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#define PNP_IDX_DRQ1 0x75
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#define PNP_IDX_MSC0 0xf0
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#define PNP_IDX_MSC1 0xf1
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#endif /* DEVICE_PNP_DEF_H */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#ifndef PART_FALLBACK_BOOT_H
|
||||
#define PART_FALLBACK_BOOT_H
|
||||
#ifndef FALLBACK_H
|
||||
#define FALLBACK_H
|
||||
|
||||
#ifndef ASSEMBLY
|
||||
|
||||
|
|
@ -15,4 +15,4 @@ void boot_successful(void);
|
|||
|
||||
#define RTC_BOOT_BYTE 48
|
||||
|
||||
#endif /* PART_FALLBACK_BOOT_H */
|
||||
#endif /* FALLBACK_H */
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
#ifndef PART_INIT_TIMER_H
|
||||
#define PART_DELAY_H
|
||||
|
||||
#if CONFIG_HAVE_INIT_TIMER == 1
|
||||
void init_timer(void);
|
||||
#else
|
||||
#define init_timer() do{} while(0)
|
||||
#endif
|
||||
|
||||
#endif /* PART_INIT_TIMER_H */
|
||||
|
|
@ -1,11 +1,11 @@
|
|||
#ifndef PART_HARD_RESET_H
|
||||
#define PART_HARD_RESET_H
|
||||
#ifndef RESET_H
|
||||
#define RESET_H
|
||||
|
||||
#if CONFIG_HAVE_HARD_RESET == 1
|
||||
void hard_reset(void);
|
||||
#else
|
||||
#define hard_reset() do {} while(0)
|
||||
#endif
|
||||
|
||||
void soft_reset(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
#ifndef PART_WATCHDOG_H
|
||||
#define PART_WATCHDOG_H
|
||||
#ifndef WATCHDOG_H
|
||||
#define WATCHDOG_H
|
||||
|
||||
#if CONFIG_USE_WATCHDOG_ON_BOOT == 1
|
||||
void watchdog_off(void);
|
||||
|
|
@ -7,4 +7,4 @@ void watchdog_off(void);
|
|||
#define watchdog_off()
|
||||
#endif
|
||||
|
||||
#endif /* PART_WATCHDOG_H */
|
||||
#endif /* WATCHDOG_H */
|
||||
|
|
@ -184,7 +184,7 @@ void cbmem_initialize(void)
|
|||
if (acpi_slp_type == 3) {
|
||||
if (!cbmem_reinit(high_tables_base)) {
|
||||
/* Something went wrong, our high memory area got wiped */
|
||||
acpi_slp_type == 0;
|
||||
acpi_slp_type = 0;
|
||||
cbmem_init(high_tables_base, high_tables_size);
|
||||
}
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#include <console/console.h>
|
||||
#include <part/fallback_boot.h>
|
||||
#include <part/watchdog.h>
|
||||
#include <fallback.h>
|
||||
#include <watchdog.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <arch/io.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ static void ram_fill(unsigned long start, unsigned long stop)
|
|||
* Fill.
|
||||
*/
|
||||
#if CONFIG_USE_PRINTK_IN_CAR
|
||||
printk_debug("DRAM fill: 0x%08x-0x%08x\r\n", start, stop);
|
||||
printk_debug("DRAM fill: 0x%08lx-0x%08lx\r\n", start, stop);
|
||||
#else
|
||||
print_debug("DRAM fill: ");
|
||||
print_debug_hex32(start);
|
||||
|
|
@ -42,7 +42,7 @@ static void ram_fill(unsigned long start, unsigned long stop)
|
|||
/* Display address being filled */
|
||||
if (!(addr & 0xfffff)) {
|
||||
#if CONFIG_USE_PRINTK_IN_CAR
|
||||
printk_debug("%08x \r", addr);
|
||||
printk_debug("%08lx \r", addr);
|
||||
#else
|
||||
print_debug_hex32(addr);
|
||||
print_debug(" \r");
|
||||
|
|
@ -52,7 +52,7 @@ static void ram_fill(unsigned long start, unsigned long stop)
|
|||
};
|
||||
/* Display final address */
|
||||
#if CONFIG_USE_PRINTK_IN_CAR
|
||||
printk_debug("%08x\r\nDRAM filled\r\n", addr);
|
||||
printk_debug("%08lx\r\nDRAM filled\r\n", addr);
|
||||
#else
|
||||
print_debug_hex32(addr);
|
||||
print_debug("\r\nDRAM filled\r\n");
|
||||
|
|
@ -67,7 +67,7 @@ static void ram_verify(unsigned long start, unsigned long stop)
|
|||
* Verify.
|
||||
*/
|
||||
#if CONFIG_USE_PRINTK_IN_CAR
|
||||
printk_debug("DRAM verify: 0x%08x-0x%08x\r\n", start, stop);
|
||||
printk_debug("DRAM verify: 0x%08lx-0x%08lx\r\n", start, stop);
|
||||
#else
|
||||
print_debug("DRAM verify: ");
|
||||
print_debug_hex32(start);
|
||||
|
|
@ -80,7 +80,7 @@ static void ram_verify(unsigned long start, unsigned long stop)
|
|||
/* Display address being tested */
|
||||
if (!(addr & 0xfffff)) {
|
||||
#if CONFIG_USE_PRINTK_IN_CAR
|
||||
printk_debug("%08x \r", addr);
|
||||
printk_debug("%08lx \r", addr);
|
||||
#else
|
||||
print_debug_hex32(addr);
|
||||
print_debug(" \r");
|
||||
|
|
@ -90,7 +90,7 @@ static void ram_verify(unsigned long start, unsigned long stop)
|
|||
if (value != addr) {
|
||||
/* Display address with error */
|
||||
#if CONFIG_USE_PRINTK_IN_CAR
|
||||
printk_err("Fail: @0x%08x Read value=0x%08x\r\n", addr, value);
|
||||
printk_err("Fail: @0x%08lx Read value=0x%08lx\r\n", addr, value);
|
||||
#else
|
||||
print_err("Fail: @0x");
|
||||
print_err_hex32(addr);
|
||||
|
|
@ -111,7 +111,7 @@ static void ram_verify(unsigned long start, unsigned long stop)
|
|||
}
|
||||
/* Display final address */
|
||||
#if CONFIG_USE_PRINTK_IN_CAR
|
||||
printk_debug("%08x", addr);
|
||||
printk_debug("%08lx", addr);
|
||||
#else
|
||||
print_debug_hex32(addr);
|
||||
#endif
|
||||
|
|
@ -142,7 +142,7 @@ void ram_check(unsigned long start, unsigned long stop)
|
|||
* are tested. -Tyson
|
||||
*/
|
||||
#if CONFIG_USE_PRINTK_IN_CAR
|
||||
printk_debug("Testing DRAM : %08x - %08x\r\n", start, stop);
|
||||
printk_debug("Testing DRAM : %08lx - %08lx\r\n", start, stop);
|
||||
#else
|
||||
print_debug("Testing DRAM : ");
|
||||
print_debug_hex32(start);
|
||||
|
|
|
|||
|
|
@ -91,3 +91,9 @@ config MAX_PHYSICAL_CPUS
|
|||
int
|
||||
default 2
|
||||
depends on BOARD_INTEL_D945GCLF
|
||||
|
||||
config HAVE_ACPI_SLIC
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_INTEL_D945GCLF
|
||||
|
||||
|
|
|
|||
|
|
@ -35,8 +35,6 @@ extern unsigned char AmlCode[];
|
|||
#if CONFIG_HAVE_ACPI_SLIC
|
||||
unsigned long acpi_create_slic(unsigned long current);
|
||||
#endif
|
||||
void generate_cpu_entries(void); // from cpu/intel/speedstep
|
||||
unsigned long acpi_fill_mcfg(unsigned long current); // from northbridge/intel/i945
|
||||
|
||||
#if OLD_ACPI
|
||||
typedef struct acpi_oemb {
|
||||
|
|
|
|||
|
|
@ -76,3 +76,9 @@ config FALLBACK_VGA_BIOS_FILE
|
|||
string
|
||||
default "amipci_01.20"
|
||||
depends on BOARD_KONTRON_986LCD_M
|
||||
|
||||
config HAVE_ACPI_SLIC
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_KONTRON_986LCD_M
|
||||
|
||||
|
|
|
|||
|
|
@ -32,10 +32,9 @@
|
|||
#include "dmi.h"
|
||||
|
||||
extern unsigned char AmlCode[];
|
||||
#if HAVE_ACPI_SLIC
|
||||
#if CONFIG_HAVE_ACPI_SLIC
|
||||
unsigned long acpi_create_slic(unsigned long current);
|
||||
#endif
|
||||
void generate_cpu_entries(void); // from cpu/intel/speedstep
|
||||
|
||||
#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h"
|
||||
static void acpi_create_gnvs(global_nvs_t *gnvs)
|
||||
|
|
@ -142,7 +141,7 @@ unsigned long write_acpi_tables(unsigned long start)
|
|||
acpi_mcfg_t *mcfg;
|
||||
acpi_fadt_t *fadt;
|
||||
acpi_facs_t *facs;
|
||||
#if HAVE_ACPI_SLIC
|
||||
#if CONFIG_HAVE_ACPI_SLIC
|
||||
acpi_header_t *slic;
|
||||
#endif
|
||||
acpi_header_t *ssdt;
|
||||
|
|
@ -216,14 +215,14 @@ unsigned long write_acpi_tables(unsigned long start)
|
|||
/* Pack GNVS into the ACPI table area */
|
||||
for (i=0; i < dsdt->length; i++) {
|
||||
if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
|
||||
printk_debug("ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, current);
|
||||
printk_debug("ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
|
||||
*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* And fill it */
|
||||
acpi_create_gnvs(current);
|
||||
acpi_create_gnvs((global_nvs_t *)current);
|
||||
|
||||
current += 0x100;
|
||||
ALIGN_CURRENT;
|
||||
|
|
@ -238,7 +237,7 @@ unsigned long write_acpi_tables(unsigned long start)
|
|||
printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt,
|
||||
dsdt->length);
|
||||
|
||||
#if HAVE_ACPI_SLIC
|
||||
#if CONFIG_HAVE_ACPI_SLIC
|
||||
printk_debug("ACPI: * SLIC\n");
|
||||
slic = (acpi_header_t *)current;
|
||||
current += acpi_create_slic(current);
|
||||
|
|
|
|||
|
|
@ -102,6 +102,7 @@ chip northbridge/intel/i945
|
|||
device pnp 4e.3 on # COM4
|
||||
io 0x60 = 0x2e8
|
||||
irq 0x70 = 10
|
||||
irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
|
||||
end
|
||||
device pnp 4e.5 off # Keyboard
|
||||
end
|
||||
|
|
|
|||
|
|
@ -26,10 +26,9 @@
|
|||
#include <x86emu/x86emu.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/coreboot_tables.h>
|
||||
#include "chip.h"
|
||||
|
||||
int add_northbridge_resources(struct lb_memory *mem);
|
||||
|
||||
int add_mainboard_resources(struct lb_memory *mem)
|
||||
{
|
||||
return add_northbridge_resources(mem);
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@
|
|||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
|
||||
void *smp_write_config_table(void *v)
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "COREBOOT";
|
||||
|
|
@ -36,6 +36,7 @@ void *smp_write_config_table(void *v)
|
|||
struct device *riser = NULL, *firewire = NULL;
|
||||
int i;
|
||||
int max_pci_bus, firewire_bus = 0, riser_bus = 0, isa_bus;
|
||||
int ioapic_id;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
|
@ -86,58 +87,65 @@ void *smp_write_config_table(void *v)
|
|||
smp_write_bus(mc, isa_bus, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
|
||||
ioapic_id = 2;
|
||||
smp_write_ioapic(mc, ioapic_id, 0x20, 0xfec00000);
|
||||
|
||||
/* Legacy Interrupts */
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, 0x2, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, 0x2, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, 0x2, 0x4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, 0x2, 0x8);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, 0x2, 0x9);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, 0x2, 0xa);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, 0x2, 0xb);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, 0x2, 0xc);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, 0x2, 0xd);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, 0x2, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, 0x2, 0xf);
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, ioapic_id, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, ioapic_id, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, ioapic_id, 0x4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, ioapic_id, 0x8);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, ioapic_id, 0x9);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, ioapic_id, 0xa);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, ioapic_id, 0xb);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, ioapic_id, 0xc);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, ioapic_id, 0xd);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, ioapic_id, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, ioapic_id, 0xf);
|
||||
|
||||
/* Builtin devices on Bus 0 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4, ioapic_id, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, ioapic_id, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, ioapic_id, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, ioapic_id, 0x17);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, ioapic_id, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, ioapic_id, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, ioapic_id, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, ioapic_id, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, ioapic_id, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, ioapic_id, 0x11);
|
||||
|
||||
/* Firewire 4:0.0 */
|
||||
/* Internal PCI bus (Firewire, PCI slot) */
|
||||
if (firewire) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x0, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x0, ioapic_id, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x4, ioapic_id, 0x14);
|
||||
}
|
||||
|
||||
if (riser) {
|
||||
/* Old riser card */
|
||||
// riser slot top 5:8.0
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, 0x2, 0x14);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14);
|
||||
// riser slot middle 5:9.0
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, 0x2, 0x15);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15);
|
||||
// riser slot bottom 5:a.0
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, 0x2, 0x16);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16);
|
||||
|
||||
/* New Riser Card */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x30, 0x2, 0x14);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x34, 0x2, 0x15);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x38, 0x2, 0x16);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x30, ioapic_id, 0x14);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x34, ioapic_id, 0x15);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x38, ioapic_id, 0x16);
|
||||
}
|
||||
|
||||
/* PCIe slot */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, ioapic_id, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1, ioapic_id, 0x11);
|
||||
|
||||
/* Onboard Ethernet */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10);
|
||||
|
||||
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
|
||||
|
|
@ -152,9 +160,26 @@ void *smp_write_config_table(void *v)
|
|||
return smp_next_mpe_entry(mc);
|
||||
}
|
||||
|
||||
/* MP table generation in coreboot is not very well designed;
|
||||
* One of the issues is that it knows nothing about Virtual
|
||||
* Wire mode, which everyone uses since a decade or so. This
|
||||
* function fixes up our floating table. This spares us doing
|
||||
* a half-baked fix of adding a new parameter to 200+ calls
|
||||
* to smp_write_floating_table()
|
||||
*/
|
||||
static void fixup_virtual_wire(void *v)
|
||||
{
|
||||
struct intel_mp_floating *mf = v;
|
||||
|
||||
mf->mpf_checksum = 0;
|
||||
mf->mpf_feature2 = MP_FEATURE_VIRTUALWIRE;
|
||||
mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr);
|
||||
fixup_virtual_wire(v);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2007-2010 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
|
|
@ -48,6 +48,7 @@
|
|||
#include "option_table.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
|
||||
#include <console/console.h>
|
||||
#include "pc80/serial.c"
|
||||
#include "arch/i386/lib/console.c"
|
||||
#include <cpu/x86/bist.h>
|
||||
|
|
@ -367,6 +368,8 @@ static void early_ich7_init(void)
|
|||
//
|
||||
#include "lib/cbmem.c"
|
||||
|
||||
#include "cpu/intel/model_6ex/cache_as_ram_disable.c"
|
||||
|
||||
void real_main(unsigned long bist)
|
||||
{
|
||||
u32 reg32;
|
||||
|
|
@ -477,7 +480,7 @@ void real_main(unsigned long bist)
|
|||
* day.
|
||||
*/
|
||||
if (resume_backup_memory)
|
||||
memcpy(resume_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
|
||||
memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
|
||||
|
||||
/* Magic for S3 resume */
|
||||
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
|
||||
|
|
@ -485,4 +488,3 @@ void real_main(unsigned long bist)
|
|||
#endif
|
||||
}
|
||||
|
||||
#include "cpu/intel/model_6ex/cache_as_ram_disable.c"
|
||||
|
|
|
|||
|
|
@ -73,3 +73,9 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
|||
hex
|
||||
default 0x6886
|
||||
depends on BOARD_RODA_RK886EX
|
||||
|
||||
config HAVE_ACPI_SLIC
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_RODA_RK886EX
|
||||
|
||||
|
|
|
|||
|
|
@ -34,8 +34,6 @@ extern unsigned char AmlCode[];
|
|||
#if CONFIG_HAVE_ACPI_SLIC
|
||||
unsigned long acpi_create_slic(unsigned long current);
|
||||
#endif
|
||||
void generate_cpu_entries(void); // from cpu/intel/speedstep
|
||||
unsigned long acpi_fill_mcfg(unsigned long current); // from northbridge/intel/i945
|
||||
|
||||
#define OLD_ACPI 0
|
||||
#if OLD_ACPI
|
||||
|
|
|
|||
|
|
@ -39,7 +39,6 @@ extern unsigned char AmlCode_dsdt[];
|
|||
extern unsigned char AmlCode_ssdt[];
|
||||
|
||||
extern u32 wake_vec;
|
||||
extern u8 acpi_sleep_type;
|
||||
|
||||
/*
|
||||
* These four macros are copied from <arch/smp/mpspec.h>, I have to do this
|
||||
|
|
@ -203,7 +202,3 @@ unsigned long write_acpi_tables(unsigned long start)
|
|||
return current;
|
||||
}
|
||||
|
||||
int acpi_is_wakeup(void)
|
||||
{
|
||||
return (acpi_sleep_type == 3);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -31,7 +31,6 @@
|
|||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <delay.h>
|
||||
#include <part/init_timer.h> /* for jason_tsc_count_end */
|
||||
#include "wakeup.h"
|
||||
|
||||
int enable_a20(void);
|
||||
|
|
|
|||
|
|
@ -30,7 +30,6 @@
|
|||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <part/hard_reset.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <bitops.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <part/hard_reset.h>
|
||||
#include <reset.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <bitops.h>
|
||||
#include <cpu/amd/model_fxx_rev.h>
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
#include <device/pciexp.h>
|
||||
#include <arch/io.h>
|
||||
#include "chip.h"
|
||||
#include <part/hard_reset.h>
|
||||
#include <reset.h>
|
||||
|
||||
typedef struct northbridge_intel_e7520_config config_t;
|
||||
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
#include <device/pciexp.h>
|
||||
#include <arch/io.h>
|
||||
#include "chip.h"
|
||||
#include <part/hard_reset.h>
|
||||
#include <reset.h>
|
||||
|
||||
typedef struct northbridge_intel_i3100_config config_t;
|
||||
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
#include <device/pciexp.h>
|
||||
#include <arch/io.h>
|
||||
#include "chip.h"
|
||||
#include <part/hard_reset.h>
|
||||
#include <reset.h>
|
||||
|
||||
typedef struct northbridge_intel_i3100_config config_t;
|
||||
|
||||
|
|
|
|||
|
|
@ -31,8 +31,9 @@
|
|||
#include <boot/tables.h>
|
||||
#include "chip.h"
|
||||
#include "i945.h"
|
||||
#include <arch/coreboot_tables.h>
|
||||
|
||||
int get_pcie_bar(u32 *base, u32 *len)
|
||||
static int get_pcie_bar(u32 *base, u32 *len)
|
||||
{
|
||||
device_t dev;
|
||||
u32 pciexbar_reg;
|
||||
|
|
|
|||
|
|
@ -398,12 +398,8 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
|
|||
die("No memory installed.\n");
|
||||
}
|
||||
|
||||
/* The chipset might be able to do this. What the heck, legacy bios
|
||||
* just beeps when a single DIMM is in the Channel 1 socket. So let's
|
||||
* not bother until someone needs this enough to cope with it.
|
||||
*/
|
||||
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
|
||||
printk_err("Channel 0 has no memory populated. This setup is not usable. Please move the DIMM.\n");
|
||||
printk_info("Channel 0 has no memory populated.\n");
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -454,7 +450,7 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8
|
|||
{
|
||||
int i, j, idx;
|
||||
int lowest_common_cas = 0;
|
||||
int max_ram_speed;
|
||||
int max_ram_speed = 0;
|
||||
|
||||
const u8 ddr2_speeds_table[] = {
|
||||
0x50, 0x60, /* DDR2 400: tCLK = 5.0ns tAC = 0.6ns */
|
||||
|
|
@ -1593,7 +1589,7 @@ static void sdram_set_bank_architecture(struct sys_info *sysinfo)
|
|||
if (sysinfo->banks[i] != 8)
|
||||
continue;
|
||||
|
||||
printk_spew("DIMM%d has 8 banks.\n");
|
||||
printk_spew("DIMM%d has 8 banks.\n", i);
|
||||
|
||||
if (i & 1)
|
||||
MCHBAR16(off32) |= 0x50;
|
||||
|
|
@ -2572,7 +2568,7 @@ static void sdram_power_management(struct sys_info *sysinfo)
|
|||
reg8 |= (1 << 2);
|
||||
pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8);
|
||||
|
||||
#if C2_SELF_REFRESH_DISABLE
|
||||
#ifdef C2_SELF_REFRESH_DISABLE
|
||||
|
||||
if (integrated_graphics) {
|
||||
printk_debug("C2 self-refresh with IGD\n");
|
||||
|
|
|
|||
|
|
@ -67,4 +67,6 @@ struct sys_info {
|
|||
|
||||
} __attribute__ ((packed));
|
||||
|
||||
void receive_enable_adjust(struct sys_info *sysinfo);
|
||||
|
||||
#endif /* RAMINIT_H */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#include <pc80/mc146818rtc.h>
|
||||
#include <part/fallback_boot.h>
|
||||
#include <fallback.h>
|
||||
|
||||
#ifndef CONFIG_MAX_REBOOT_CNT
|
||||
#error "CONFIG_MAX_REBOOT_CNT not defined"
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
#include <part/fallback_boot.h>
|
||||
|
||||
/* Base Address */
|
||||
#ifndef CONFIG_TTYS0_BASE
|
||||
#define CONFIG_TTYS0_BASE 0x3f8
|
||||
|
|
|
|||
|
|
@ -15,7 +15,6 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <part/fallback_boot.h>
|
||||
#include "../lib/usbdebug_direct.c"
|
||||
|
||||
static void early_usbdebug_direct_init(void)
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
#include <device/pciexp.h>
|
||||
#include <arch/io.h>
|
||||
#include "chip.h"
|
||||
#include <part/hard_reset.h>
|
||||
#include <reset.h>
|
||||
|
||||
#define PCIE_LCTL 0x50
|
||||
#define PCIE_LSTS 0x52
|
||||
|
|
|
|||
|
|
@ -20,4 +20,5 @@
|
|||
config SOUTHBRIDGE_INTEL_I82801GX
|
||||
bool
|
||||
select IOAPIC
|
||||
select USE_WATCHDOG_ON_BOOT
|
||||
|
||||
|
|
|
|||
|
|
@ -47,6 +47,24 @@
|
|||
extern void i82801gx_enable(device_t dev);
|
||||
#endif
|
||||
|
||||
#define MAINBOARD_POWER_OFF 0
|
||||
#define MAINBOARD_POWER_ON 1
|
||||
#define MAINBOARD_POWER_KEEP 2
|
||||
|
||||
#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
|
||||
#endif
|
||||
|
||||
/* PCI Configuration Space (D30:F0): PCI2PCI */
|
||||
#define PSTS 0x06
|
||||
#define SMLT 0x1b
|
||||
#define SECSTS 0x1e
|
||||
#define INTR 0x3c
|
||||
#define BCTRL 0x3e
|
||||
#define SBR (1 << 6)
|
||||
#define SEE (1 << 1)
|
||||
#define PERE (1 << 0)
|
||||
|
||||
/* PCI Configuration Space (D31:F0): LPC */
|
||||
|
||||
#define SERIRQ_CNTL 0x64
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@
|
|||
|
||||
typedef struct southbridge_intel_i82801gx_config config_t;
|
||||
|
||||
static int set_bits(u8 * port, u32 mask, u32 val)
|
||||
static int set_bits(u32 port, u32 mask, u32 val)
|
||||
{
|
||||
u32 reg32;
|
||||
int count;
|
||||
|
|
@ -62,7 +62,7 @@ static int set_bits(u8 * port, u32 mask, u32 val)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int codec_detect(u8 * base)
|
||||
static int codec_detect(u32 base)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
|
|
@ -116,7 +116,7 @@ static u32 find_verb(struct device *dev, u32 viddid, u32 ** verb)
|
|||
* no response would imply that the codec is non-operative
|
||||
*/
|
||||
|
||||
static int wait_for_ready(u8 *base)
|
||||
static int wait_for_ready(u32 base)
|
||||
{
|
||||
/* Use a 50 usec timeout - the Linux kernel uses the
|
||||
* same duration */
|
||||
|
|
@ -139,7 +139,7 @@ static int wait_for_ready(u8 *base)
|
|||
* is non-operative
|
||||
*/
|
||||
|
||||
static int wait_for_valid(u8 *base)
|
||||
static int wait_for_valid(u32 base)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
|
|
@ -163,7 +163,7 @@ static int wait_for_valid(u8 *base)
|
|||
return -1;
|
||||
}
|
||||
|
||||
static void codec_init(struct device *dev, u8 * base, int addr)
|
||||
static void codec_init(struct device *dev, u32 base, int addr)
|
||||
{
|
||||
u32 reg32;
|
||||
u32 *verb;
|
||||
|
|
@ -207,7 +207,7 @@ static void codec_init(struct device *dev, u8 * base, int addr)
|
|||
printk_debug("Azalia: verb loaded.\n");
|
||||
}
|
||||
|
||||
static void codecs_init(struct device *dev, u8 * base, u32 codec_mask)
|
||||
static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
|
||||
{
|
||||
int i;
|
||||
for (i = 2; i >= 0; i--) {
|
||||
|
|
@ -218,7 +218,7 @@ static void codecs_init(struct device *dev, u8 * base, u32 codec_mask)
|
|||
|
||||
static void azalia_init(struct device *dev)
|
||||
{
|
||||
u8 *base;
|
||||
u32 base;
|
||||
struct resource *res;
|
||||
u32 codec_mask;
|
||||
u8 reg8;
|
||||
|
|
@ -303,7 +303,7 @@ static void azalia_init(struct device *dev)
|
|||
|
||||
// NOTE this will break as soon as the Azalia get's a bar above
|
||||
// 4G. Is there anything we can do about it?
|
||||
base = (u8 *) ((u32)res->base);
|
||||
base = (u32)res->base;
|
||||
printk_debug("Azalia: base = %08x\n", (u32)base);
|
||||
codec_mask = codec_detect(base);
|
||||
|
||||
|
|
|
|||
|
|
@ -27,7 +27,6 @@
|
|||
#include <pc80/i8259.h>
|
||||
#include <arch/io.h>
|
||||
#include "i82801gx.h"
|
||||
#include "i82801gx_power.h"
|
||||
|
||||
#define NMI_OFF 0
|
||||
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include "i82801gx.h"
|
||||
|
||||
static void pci_init(struct device *dev)
|
||||
{
|
||||
|
|
@ -34,31 +35,31 @@ static void pci_init(struct device *dev)
|
|||
pci_write_config16(dev, PCI_COMMAND, reg16);
|
||||
|
||||
/* This device has no interrupt */
|
||||
pci_write_config8(dev, 0x3c, 0xff);
|
||||
pci_write_config8(dev, INTR, 0xff);
|
||||
|
||||
/* disable parity error response and SERR */
|
||||
reg16 = pci_read_config16(dev, 0x3e);
|
||||
reg16 = pci_read_config16(dev, BCTRL);
|
||||
reg16 &= ~(1 << 0);
|
||||
reg16 &= ~(1 << 1);
|
||||
pci_write_config16(dev, 0x3e, reg16);
|
||||
pci_write_config16(dev, BCTRL, reg16);
|
||||
|
||||
/* Master Latency Count must be set to 0x04! */
|
||||
reg8 = pci_read_config8(dev, 0x1b);
|
||||
reg8 = pci_read_config8(dev, SMLT);
|
||||
reg8 &= 0x07;
|
||||
reg8 |= (0x04 << 3);
|
||||
pci_write_config8(dev, 0x1b, reg8);
|
||||
pci_write_config8(dev, SMLT, reg8);
|
||||
|
||||
/* Will this improve throughput of bus masters? */
|
||||
pci_write_config8(dev, PCI_MIN_GNT, 0x06);
|
||||
|
||||
/* Clear errors in status registers */
|
||||
reg16 = pci_read_config16(dev, 0x06);
|
||||
reg16 = pci_read_config16(dev, PSTS);
|
||||
//reg16 |= 0xf900;
|
||||
pci_write_config16(dev, 0x06, reg16);
|
||||
pci_write_config16(dev, PSTS, reg16);
|
||||
|
||||
reg16 = pci_read_config16(dev, 0x1e);
|
||||
reg16 = pci_read_config16(dev, SECSTS);
|
||||
// reg16 |= 0xf900;
|
||||
pci_write_config16(dev, 0x1e, reg16);
|
||||
pci_write_config16(dev, SECSTS, reg16);
|
||||
}
|
||||
|
||||
#undef PCI_BRIDGE_UPDATE_COMMAND
|
||||
|
|
|
|||
|
|
@ -75,7 +75,7 @@ static void pci_init(struct device *dev)
|
|||
reg16 |= (1 << 6);
|
||||
pci_write_config16(dev, 0x50, reg16);
|
||||
|
||||
#if EVEN_MORE_DEBUG
|
||||
#ifdef EVEN_MORE_DEBUG
|
||||
reg32 = pci_read_config32(dev, 0x20);
|
||||
printk_spew(" MBL = 0x%08x\n", reg32);
|
||||
reg32 = pci_read_config32(dev, 0x24);
|
||||
|
|
|
|||
|
|
@ -1,27 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#define MAINBOARD_POWER_OFF 0
|
||||
#define MAINBOARD_POWER_ON 1
|
||||
#define MAINBOARD_POWER_KEEP 2
|
||||
|
||||
#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
|
||||
#endif
|
||||
|
||||
|
|
@ -19,6 +19,7 @@
|
|||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <reset.h>
|
||||
|
||||
void soft_reset(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
#include <device/pci.h>
|
||||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <string.h>
|
||||
|
|
@ -237,7 +238,7 @@ static void smi_set_eos(void)
|
|||
|
||||
extern uint8_t smm_relocation_start, smm_relocation_end;
|
||||
|
||||
void smm_relocate(void)
|
||||
static void smm_relocate(void)
|
||||
{
|
||||
u32 smi_en;
|
||||
u16 pm1_en;
|
||||
|
|
@ -317,7 +318,7 @@ void smm_relocate(void)
|
|||
outb(0x00, 0xb2);
|
||||
}
|
||||
|
||||
void smm_install(void)
|
||||
static void smm_install(void)
|
||||
{
|
||||
/* enable the SMM memory window */
|
||||
pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
|
||||
|
|
|
|||
|
|
@ -27,7 +27,6 @@
|
|||
#include <cpu/x86/smm.h>
|
||||
#include <device/pci_def.h>
|
||||
#include "i82801gx.h"
|
||||
#include "i82801gx_power.h"
|
||||
|
||||
#define DEBUG_SMI
|
||||
|
||||
|
|
|
|||
|
|
@ -53,8 +53,8 @@ static void usb_ehci_init(struct device *dev)
|
|||
/* Clear any pending port changes */
|
||||
res = find_resource(dev, 0x10);
|
||||
base = res->base;
|
||||
reg32 = read32((u8 *)base + 0x24) | (1 << 2);
|
||||
write32((u8 *)base + 0x24, reg32);
|
||||
reg32 = read32(base + 0x24) | (1 << 2);
|
||||
write32(base + 0x24, reg32);
|
||||
|
||||
/* workaround */
|
||||
reg8 = pci_read_config8(dev, 0x84);
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#include <arch/io.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <watchdog.h>
|
||||
|
||||
void watchdog_off(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <part/hard_reset.h>
|
||||
#include <reset.h>
|
||||
|
||||
#define PCI_DEV(BUS, DEV, FN) ( \
|
||||
(((BUS) & 0xFFF) << 20) | \
|
||||
|
|
|
|||
|
|
@ -34,13 +34,9 @@
|
|||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <part/hard_reset.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <bitops.h>
|
||||
#include <cpu/amd/model_fxx_rev.h>
|
||||
|
||||
//#include "amdk8.h"
|
||||
|
||||
#include <arch/io.h>
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -102,12 +102,12 @@ static struct pnp_info pnp_dev_info[] = {
|
|||
{ &ops, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
|
||||
{ &ops, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
|
||||
{ &ops, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
|
||||
{ &ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
|
||||
{ &ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC1, { 0x7f8, 0 }, },
|
||||
/* No 4 { 0,}, */
|
||||
{ &ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
|
||||
{ &ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
|
||||
{ &ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} },
|
||||
{ &ops, W83627THG_GPIO2,},
|
||||
{ &ops, W83627THG_GPIO3,},
|
||||
{ &ops, W83627THG_GPIO3, PNP_EN | PNP_MSC0 | PNP_MSC1, },
|
||||
{ &ops, W83627THG_ACPI, PNP_IRQ0, },
|
||||
{ &ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -162,15 +162,16 @@ function create_config
|
|||
echo "CONFIG_MAINBOARD_DIR=\"$VENDOR/$MAINBOARD\"" >> .config
|
||||
if [ "$PAYLOAD" != "/dev/null" ]; then
|
||||
echo "# CONFIG_PAYLOAD_NONE is not set" >> .config
|
||||
echo "CONFIG_PAYLOAD_ELF=\"$PAYLOAD\"" >> .config
|
||||
echo "CONFIG_PAYLOAD_ELF=y" >> .config
|
||||
echo "CONFIG_FALLBACK_PAYLOAD_FILE=\"$PAYLOAD\"" >> .config
|
||||
fi
|
||||
|
||||
if [ "$loglevel" != "default" ]; then
|
||||
printf "(loglevel override) "
|
||||
echo "CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_$loglevel=y"
|
||||
echo "CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=$loglevel"
|
||||
echo "CONFIG_DEFAULT_CONSOLE_LOGLEVEL_$loglevel=y"
|
||||
echo "CONFIG_DEFAULT_CONSOLE_LOGLEVEL=$loglevel"
|
||||
echo "CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_$loglevel=y" >> .config
|
||||
echo "CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=$loglevel" >> .config
|
||||
echo "CONFIG_DEFAULT_CONSOLE_LOGLEVEL_$loglevel=y" >> .config
|
||||
echo "CONFIG_DEFAULT_CONSOLE_LOGLEVEL=$loglevel" >> .config
|
||||
fi
|
||||
fi
|
||||
|
||||
|
|
@ -223,7 +224,6 @@ function compile_target
|
|||
ret=$?
|
||||
mv .config ${build_dir}/config.build
|
||||
mv .xcompile ${build_dir}/xcompile.build
|
||||
mv ..config.tmp ${build_dir}/config.deps
|
||||
cd $TARGET/${VENDOR}_${MAINBOARD}
|
||||
etime=`perl -e 'print time();' 2>/dev/null || date +%s`
|
||||
duration=$(( $etime - $stime ))
|
||||
|
|
|
|||
|
|
@ -22449,7 +22449,10 @@ static unsigned arch_type_to_regcm(struct compile_state *state, struct type *typ
|
|||
|
||||
static int is_imm32(struct triple *imm)
|
||||
{
|
||||
return ((imm->op == OP_INTCONST) && (imm->u.cval <= 0xffffffffUL)) ||
|
||||
// second condition commented out to prevent compiler warning:
|
||||
// imm->u.cval is always 32bit unsigned, so the comparison is
|
||||
// always true.
|
||||
return ((imm->op == OP_INTCONST) /* && (imm->u.cval <= 0xffffffffUL) */ ) ||
|
||||
(imm->op == OP_ADDRCONST);
|
||||
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue