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vc/mediatek/mt8195: Improve DRAM stability by impedance tracking 

Enable the impedance tracking for channel 2 and channel 3.
The impedance tracking can compensate the settings of impedance
when the temperature changes.

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I047ab70bb59736a8ba8ae75ab15659900c784342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56620
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ryan Chuang 2021-07-23 15:56:15 +08:00 committed by Hung-Te Lin
parent 403fa86924
commit de3859d538
1 changed files with 5 additions and 1 deletions
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6
src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c
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@ -1373,7 +1373,11 @@ void DramcImpedanceTrackingEnable(DRAMC_CTX_T *p)
if (channel_num_auxadc > 2) { if (channel_num_auxadc > 2) {
vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHC_ADDR, P_Fld(0, MISC_IMPCAL_DIS_SUS_CH0_DRV) | P_Fld(1, MISC_IMPCAL_DIS_SUS_CH1_DRV)); vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHC_ADDR, P_Fld(0, MISC_IMPCAL_DIS_SUS_CH0_DRV) | P_Fld(1, MISC_IMPCAL_DIS_SUS_CH1_DRV));
vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHD_ADDR, P_Fld(1, MISC_IMPCAL_DIS_SUS_CH0_DRV) | P_Fld(0, MISC_IMPCAL_DIS_SUS_CH1_DRV)); vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHD_ADDR, P_Fld(1, MISC_IMPCAL_DIS_SUS_CH0_DRV) | P_Fld(0, MISC_IMPCAL_DIS_SUS_CH1_DRV));
} vIO32WriteFldMulti(DDRPHY_REG_MISC_CTRL0 + SHIFT_TO_CHC_ADDR, P_Fld(0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT) | P_Fld(0x0, MISC_CTRL0_IMPCAL_TRACK_DISABLE));
vIO32WriteFldMulti(DDRPHY_REG_MISC_CTRL0 + SHIFT_TO_CHD_ADDR, P_Fld(0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT) | P_Fld(0x1, MISC_CTRL0_IMPCAL_TRACK_DISABLE));
vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHC_ADDR, P_Fld(0, MISC_IMPCAL_IMPSRCEXT) | P_Fld(1, MISC_IMPCAL_IMPCAL_ECO_OPT));
vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHD_ADDR, P_Fld(1, MISC_IMPCAL_IMPSRCEXT) | P_Fld(0, MISC_IMPCAL_IMPCAL_ECO_OPT));
}
#endif #endif
//Maoauo: keep following setting for SPMFW enable REFCTRL0_DRVCGWREF = 1 (Imp SW Save mode) //Maoauo: keep following setting for SPMFW enable REFCTRL0_DRVCGWREF = 1 (Imp SW Save mode)