intel/apollolake: Add IPU to disable_dev function
The SoC has an Image Processing Unit which is located on PCI 00:03.0. There is a corresponding parameter for FSP which handles enabling/disabling of this functionality (IpuEn). Add this device to the disable_dev() function of the chip so that if this device is disabled in devicetree the matching FSP parameter will be disabled as well. As this parameter is only valid for Apollo Lake, use the config switch CONFIG_SOC_INTEL_GLK to disable this code if compiled not for Apollo Lake. As this issue is regarding a missing structure member, this check needs to be done on preprocessor level and not at runtime. Test=Verified this function on mc_apl2. Change-Id: I75444bf483de32ba641f76ca50e9744fdce2e726 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/30992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -2,7 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 - 2017 Intel Corp.
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* Copyright (C) 2017 - 2018 Siemens AG
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* Copyright (C) 2017 - 2019 Siemens AG
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
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*
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@ -522,6 +522,11 @@ static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig)
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case PCH_DEVFN_SMBUS:
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silconfig->SmbusEnable = 0;
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break;
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#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK)
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case SA_DEVFN_IPU:
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silconfig->IpuEn = 0;
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break;
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#endif
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default:
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printk(BIOS_WARNING, "PCI:%02x.%01x: Could not disable the device\n",
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PCI_SLOT(dev->path.pci.devfn),
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@ -44,6 +44,10 @@
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#define SA_DEVFN_IGD _SA_DEVFN(IGD)
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#define SA_DEV_IGD _SA_DEV(IGD)
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#define SA_DEV_SLOT_IPU 0x03
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#define SA_DEVFN_IPU _SA_DEVFN(IPU)
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#define SA_DEV_IPU _SA_DEV(IPU)
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/* PCH Devices */
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#define PCH_DEV_SLOT_NPK 0x00
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