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AMD: Fix GFXUMA with 4GB or more RAM 

Northbridge code incorrectly adjusted the last cacheable memory
resource to accomodate room for UMA framebuffer. If system had
4GB or more memory that last resource is not below 4GB and not
the one where UMA is located.

There are three consequences:

The last entry in coreboot memory table is reduced by uma_memory_size.

Due the incorrect code in northbridge code state.tomk,
end of last resource below 4GB, had not been adjusted.
Incrementing that by uma_memory_size diverts a region
possibly claimed for MMIO to RAM, as TOP_MEM is written.

Since the UMA framebuffer did not have IORESOURCE_CACHEABLE,
it was ignored from the MTRR setup and not set uncacheable.

The setting of TOP_MEM and TOP_MEM2, as well as all the MTRRs,
should be copied from BSP to all APs instead of deriving the data
separately for each Logical CPU.

Change-Id: I8e69fc8854b776fe9e4fe6ddfb101eba14888939
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1217
Tested-by: build bot (Jenkins)
Reviewed-by: Denis Carikli <GNUtoo@no-log.org>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Kyösti Mälkki 2012-07-10 13:10:24 +03:00 committed by Patrick Georgi
parent 2354515f2e
commit de3dde46fd
6 changed files with 19 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
src/cpu/amd/mtrr/amd_mtrr.c
View File

@ -102,6 +102,20 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc
}
static void uma_fb_resource(void *gp, struct device *dev, struct resource *res)
{
struct mem_state *state = gp;
unsigned long topk;
topk = resk(res->base + res->size);
if (state->tom2k < topk) {
state->tom2k = topk;
}
if ((topk < 4*1024*1024) && (state->tomk < topk)) {
state->tomk = topk;
}
}
void amd_setup_mtrrs(void)
{
unsigned long address_bits;
@ -132,6 +146,9 @@ void amd_setup_mtrrs(void)
set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
state.tomk = state.tom2k = 0;
search_global_resources(
IORESOURCE_MEM | IORESOURCE_UMA_FB, IORESOURCE_MEM | IORESOURCE_UMA_FB,
uma_fb_resource, &state);
search_global_resources(
IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
set_fixed_mtrr_resource, &state);
@ -144,13 +161,6 @@ void amd_setup_mtrrs(void)
state.tomk = (state.tomk + TOP_MEM_MASK_KB) & ~TOP_MEM_MASK_KB;
msr.hi = state.tomk >> 22;
msr.lo = state.tomk << 10;
/* If UMA graphics is enabled, the frame buffer memory
* has been deducted from the size of memory below 4GB.
* When setting TOM, include UMA DRAM
*/
#if CONFIG_GFXUMA
msr.lo += uma_memory_size;
#endif
wrmsr(TOP_MEM, msr);
/* if DRAM above 4GB: set SYSCFG_MSR_TOM2En and SYSCFG_MSR_TOM2WB */

5
src/northbridge/amd/agesa/family10/northbridge.c
View File

@ -1063,11 +1063,6 @@ static void amdfam10_domain_set_resources(device_t dev)
}
}
#if CONFIG_GFXUMA
/* Deduct uma memory before reporting because
* this is what the mtrr code expects */
sizek -= uma_memory_size / 1024;
#endif
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
#if CONFIG_WRITE_HIGH_TABLES

5
src/northbridge/amd/agesa/family15/northbridge.c
View File

@ -830,11 +830,6 @@ static void domain_set_resources(device_t dev)
}
}
#if CONFIG_GFXUMA
/* Deduct uma memory before reporting because
* this is what the mtrr code expects */
sizek -= uma_memory_size / 1024;
#endif
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
#if CONFIG_WRITE_HIGH_TABLES

5
src/northbridge/amd/agesa/family15tn/northbridge.c
View File

@ -768,11 +768,6 @@ static void domain_set_resources(device_t dev)
}
}
#if CONFIG_GFXUMA == 1
/* Deduct uma memory before reporting because
* this is what the mtrr code expects */
sizek -= uma_memory_size / 1024;
#endif
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
#if CONFIG_WRITE_HIGH_TABLES==1

5
src/northbridge/amd/amdfam10/northbridge.c
View File

@ -1095,11 +1095,6 @@ static void amdfam10_domain_set_resources(device_t dev)
}
}
#if CONFIG_GFXUMA
/* Deduct uma memory before reporting because
* this is what the mtrr code expects */
sizek -= uma_memory_size / 1024;
#endif
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
#if CONFIG_WRITE_HIGH_TABLES

12
src/northbridge/amd/amdk8/northbridge.c
View File

@ -1093,16 +1093,8 @@ static void amdk8_domain_set_resources(device_t dev)
sizek -= (4*1024*1024 - mmio_basek);
}
}
/* If sizek == 0, it was split at mmio_basek without a hole.
* Don't create an empty ram_resource.
*/
#if CONFIG_GFXUMA
/* Deduct uma memory before reporting because
* this is what the mtrr code expects */
sizek -= uma_memory_size / 1024;
#endif
if (sizek)
ram_resource(dev, (idx | i), basek, sizek);
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
#if CONFIG_WRITE_HIGH_TABLES
printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",