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cpu/amd/fam10: Drop support 

Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.

Change-Id: I3c69f158a5667783292161815f9ae61195b5e03b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36963
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-11-19 15:51:51 +01:00 committed by Kyösti Mälkki
parent eef63607b8
commit de56a66e73
41 changed files with 1 additions and 6973 deletions
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3
src/arch/x86/include/arch/cpu.h
View File

@ -210,8 +210,7 @@ int cpu_have_cpuid(void);
static inline bool cpu_is_amd(void)
{
return CONFIG(CPU_AMD_AGESA) || CONFIG(CPU_AMD_PI)
|| CONFIG(SOC_AMD_COMMON) || CONFIG(CPU_AMD_MODEL_10XXX);
return CONFIG(CPU_AMD_AGESA) || CONFIG(CPU_AMD_PI) || CONFIG(SOC_AMD_COMMON);
}
static inline bool cpu_is_intel(void)

10
src/arch/x86/smbios.c
View File

@ -545,16 +545,6 @@ static int get_socket_type(void)
return 0x13;
if (CONFIG(CPU_INTEL_SOCKET_LGA775))
return 0x15;
if (CONFIG(CPU_AMD_SOCKET_AM2R2))
return 0x17;
if (CONFIG(CPU_AMD_SOCKET_F_1207))
return 0x18;
if (CONFIG(CPU_AMD_SOCKET_G34_NON_AGESA))
return 0x1a;
if (CONFIG(CPU_AMD_SOCKET_AM3))
return 0x1b;
if (CONFIG(CPU_AMD_SOCKET_C32_NON_AGESA))
return 0x1c;
return 0x02; /* Unknown */
}

10
src/cpu/amd/Kconfig
View File

@ -1,12 +1,2 @@
source src/cpu/amd/socket_AM2r2/Kconfig
source src/cpu/amd/socket_AM3/Kconfig
source src/cpu/amd/socket_C32/Kconfig
source src/cpu/amd/socket_FM2/Kconfig
source src/cpu/amd/socket_G34/Kconfig
source src/cpu/amd/socket_ASB2/Kconfig
source src/cpu/amd/socket_F_1207/Kconfig
source src/cpu/amd/family_10h-family_15h/Kconfig
source src/cpu/amd/agesa/Kconfig
source src/cpu/amd/pi/Kconfig

8
src/cpu/amd/Makefile.inc
View File

@ -1,10 +1,2 @@
subdirs-$(CONFIG_CPU_AMD_SOCKET_F_1207) += socket_F_1207
subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2R2) += socket_AM2r2
subdirs-$(CONFIG_CPU_AMD_SOCKET_AM3) += socket_AM3
subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2
subdirs-$(CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA) += socket_C32
subdirs-$(CONFIG_CPU_AMD_SOCKET_FM2_NON_AGESA) += socket_FM2
subdirs-$(CONFIG_CPU_AMD_SOCKET_G34_NON_AGESA) += socket_G34
subdirs-$(CONFIG_CPU_AMD_AGESA) += agesa
subdirs-$(CONFIG_CPU_AMD_PI) += pi

648
src/cpu/amd/car/cache_as_ram.inc
View File

@ -1,648 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase CONFIG_DCACHE_RAM_BASE
#define CacheSizeBSPStack CONFIG_DCACHE_BSP_TOP_STACK_SIZE
#define CacheSizeBSPSlush CONFIG_DCACHE_BSP_TOP_STACK_SLUSH
/* For CAR with Fam10h. */
#define CacheSizeAPStack CONFIG_DCACHE_AP_STACK_SIZE
#define jmp_if_not_k8(x) comisd %xmm2, %xmm1; jae x
#define jmp_if_k8(x) comisd %xmm2, %xmm1; jb x
#define jmp_if_not_fam15h(x) comisd %xmm3, %xmm1; jb x
#define jmp_if_fam15h(x) comisd %xmm3, %xmm1; jae x
#define CPUID_MASK 0x0ff00f00
#define CPUID_VAL_FAM10_ROTATED 0x0f000010
#define CPUID_VAL_FAM15_ROTATED 0x0f000060
/*
* XMM map:
* xmm1: CPU family
* xmm2: Fam10h comparison value
* xmm3: Fam15h comparison value
* xmm4: Backup EBX
* xmm5: coreboot init detect
*/
/* Save the BIST result. */
movl %eax, %ebp
/*
* For normal part %ebx already contain cpu_init_detected
* from fallback call.
*/
cache_as_ram_setup:
post_code(0xa0)
/* Enable SSE. */
movl %cr4, %eax
orl $(3 << 9), %eax
movl %eax, %cr4
/* Figure out the CPU family. */
cvtsi2sd %ebx, %xmm4
movl $0x01, %eax
cpuid
/* Base family is bits 8..11, extended family is bits 20..27. */
andl $CPUID_MASK, %eax
/* Reorder bits for easier comparison by value. */
roll $0x10, %eax
cvtsi2sd %eax, %xmm1
movl $CPUID_VAL_FAM10_ROTATED, %eax
cvtsi2sd %eax, %xmm2
movl $CPUID_VAL_FAM15_ROTATED, %eax
cvtsi2sd %eax, %xmm3
cvtsd2si %xmm4, %ebx
/* Check if cpu_init_detected. */
movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
andl $MTRR_DEF_TYPE_EN, %eax
movl %eax, %ebx /* We store the status. */
cvtsi2sd %ebx, %xmm5
jmp_if_k8(CAR_FAM10_out_post_errata)
/*
* For GH, CAR need to set DRAM Base/Limit registers to direct that
* to node0.
* Only BSP needed, for other nodes set during HT/memory init.
* So we need to check if it is BSP.
*/
movl $0x1b, %ecx
rdmsr
bt $8, %eax /* BSP */
jnc CAR_FAM10_out
/* Enable RT tables on BSP. */
movl $0x8000c06c, %eax
movw $0xcf8, %dx
outl %eax, %dx
addw $4, %dx
inl %dx, %eax
btr $0, %eax
outl %eax, %dx
/* Setup temporary DRAM map: [0,16M) bit 0-23. */
movl $0x8000c144, %eax
movw $0xcf8, %dx
outl %eax, %dx
addw $4, %dx
movl $0, %eax
outl %eax, %dx
movl $0x8000c140, %eax
movw $0xcf8, %dx
outl %eax, %dx
addw $4, %dx
movl $3, %eax
outl %eax, %dx
CAR_FAM10_out:
jmp_if_fam15h(CAR_FAM10_errata_applied)
/*
* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
* Re-enable it in after RAM is initialized and before CAR is disabled.
*/
movl $BU_CFG2_MSR, %ecx
rdmsr
bts $15, %eax /* Set bit 15 in EDX:EAX (bit 15 in EAX). */
wrmsr
/* Erratum 343, RevGuide for Fam10h, Pub#41322 Rev. 3.33 */
movl $BU_CFG2_MSR, %ecx
rdmsr
bts $35-32, %edx /* Set bit 35 in EDX:EAX (bit 3 in EDX). */
wrmsr
CAR_FAM10_errata_applied:
#if CONFIG(MMCONF_SUPPORT)
#if (CONFIG_MMCONF_BASE_ADDRESS > 0xFFFFFFFF)
#error "MMCONF_BASE_ADDRESS too big"
#elif (CONFIG_MMCONF_BASE_ADDRESS & 0xFFFFF)
#error "MMCONF_BASE_ADDRESS not 1MB aligned"
#endif
movl $0, %edx
movl $((CONFIG_MMCONF_BASE_ADDRESS) | (1 << 0)), %eax
#if (CONFIG_MMCONF_BUS_NUMBER == 1)
#elif (CONFIG_MMCONF_BUS_NUMBER == 2)
orl $(1 << 2), %eax
#elif (CONFIG_MMCONF_BUS_NUMBER == 4)
orl $(2 << 2), %eax
#elif (CONFIG_MMCONF_BUS_NUMBER == 8)
orl $(3 << 2), %eax
#elif (CONFIG_MMCONF_BUS_NUMBER == 16)
orl $(4 << 2), %eax
#elif (CONFIG_MMCONF_BUS_NUMBER == 32)
orl $(5 << 2), %eax
#elif (CONFIG_MMCONF_BUS_NUMBER == 64)
orl $(6 << 2), %eax
#elif (CONFIG_MMCONF_BUS_NUMBER == 128)
orl $(7 << 2), %eax
#elif (CONFIG_MMCONF_BUS_NUMBER == 256)
orl $(8 << 2), %eax
#else
#error "bad MMCONF_BUS_NUMBER value"
#endif
movl $MMIO_CONF_BASE, %ecx
wrmsr
#endif
CAR_FAM10_out_post_errata:
/* Fam15h APIC IDs do not depend on NB config bit 54 */
jmp_if_not_fam15h(skip_nb54_set)
movl $NB_CFG_MSR, %ecx
rdmsr
bts $(54 - 32), %edx /* Set NB config bit 54 */
wrmsr
skip_nb54_set:
/* On Fam15h CPUs each compute unit's MTRRs are shared between two cores */
jmp_if_not_fam15h(skip_cu_check)
/* Get the initial APIC ID. */
movl $1, %eax
cpuid
movl %ebx, %eax
/* Restore init detect */
cvtsd2si %xmm5, %ebx
/* Determine if this is the second core to start in a compute unit; if so, wait for first core start, clear init detect and skip MTRR init */
bt $24, %eax
jnc skip_cu_check /* First core in the compute unit jumps to skip_cu_check */
/* Determine if this is the second core to start in a compute unit; if so, clear init detect and skip MTRR init */
/* Busywait until the first core sets up the MTRRs */
check_init_detect_1:
/* Check if cpu_init_detected. */
movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
andl $MTRR_DEF_TYPE_EN, %eax
cmp $0x00000000, %eax
je check_init_detect_1 /* First core has not yet started */
check_init_detect_2:
movl $SYSCFG_MSR, %ecx
rdmsr
andl $(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn), %eax
cmp $0x00000000, %eax
je check_init_detect_2 /* First core has not yet started */
/* First core has now started */
movl $0x00000000, %ebx /* Clear init detect flag */
cvtsi2sd %ebx, %xmm5
jmp fam10_mtrr_setup_complete
skip_cu_check:
jmp_if_not_fam15h(CAR_FAM15_errata_applied)
/* Erratum 714, RevGuide for Fam15h, Pub#48063 Rev. 3.24 */
movl $BU_CFG2_MSR, %ecx
rdmsr
bts $8, %eax /* Set bit 8 in EDX:EAX (bit 8 in EAX). */
wrmsr
CAR_FAM15_errata_applied:
/* Set MtrrFixDramModEn for clear fixed MTRR. */
enable_fixed_mtrr_dram_modify:
movl $SYSCFG_MSR, %ecx
rdmsr
andl $(~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn)), %eax
orl $SYSCFG_MSR_MtrrFixDramModEn, %eax
wrmsr
/* Clear all MTRRs. */
xorl %edx, %edx
movl $all_mtrr_msrs, %esi
clear_fixed_var_mtrr:
lodsl (%esi), %eax
testl %eax, %eax
jz clear_fixed_var_mtrr_out
movl %eax, %ecx
xorl %eax, %eax
wrmsr
jmp clear_fixed_var_mtrr
clear_fixed_var_mtrr_out:
/*
* 0x06 is the WB IO type for a given 4k segment.
* 0x1e is the MEM IO type for a given 4k segment (K10 and above).
* segs is the number of 4k segments in the area of the particular
* register we want to use for CAR.
* reg is the register where the IO type should be stored.
*/
.macro extractmask segs, reg
.if \segs <= 0
/*
* The xorl here is superfluous because at the point of first execution
* of this macro, %eax and %edx are cleared. Later invocations of this
* macro will have a monotonically increasing segs parameter.
*/
xorl \reg, \reg
.else
jmp_if_k8(1f)
.if \segs == 1
movl $0x1e000000, \reg /* WB MEM type */
.elseif \segs == 2
movl $0x1e1e0000, \reg /* WB MEM type */
.elseif \segs == 3
movl $0x1e1e1e00, \reg /* WB MEM type */
.elseif \segs >= 4
movl $0x1e1e1e1e, \reg /* WB MEM type */
.endif
jmp 2f
1:
.if \segs == 1
movl $0x06000000, \reg /* WB IO type */
.elseif \segs == 2
movl $0x06060000, \reg /* WB IO type */
.elseif \segs == 3
movl $0x06060600, \reg /* WB IO type */
.elseif \segs >= 4
movl $0x06060606, \reg /* WB IO type */
.endif
2:
.endif /* if \segs <= 0 */
.endm
/*
* carsize is the cache size in bytes we want to use for CAR.
* windowoffset is the 32k-aligned window into CAR size.
*/
.macro simplemask carsize, windowoffset
.set gas_bug_workaround,(((\carsize - \windowoffset) >> 12) - 4)
extractmask gas_bug_workaround, %eax
.set gas_bug_workaround,(((\carsize - \windowoffset) >> 12))
extractmask gas_bug_workaround, %edx
/*
* Without the gas bug workaround, the entire macro would consist
* only of the two lines below:
* extractmask (((\carsize - \windowoffset) >> 12) - 4), %eax
* extractmask (((\carsize - \windowoffset) >> 12)), %edx
*/
.endm
#if CONFIG(CPU_AMD_MODEL_10XXX)
#if CacheSize > 0x80000
#error Invalid CAR size, must be at most 128k (processor limit is 512k).
#endif
#else
#if CacheSize > 0x10000
#error Invalid CAR size, must be at most 64k.
#endif
#endif
#if CacheSize < 0x1000
#error Invalid CAR size, must be at least 4k. This is a processor limitation.
#endif
#if (CacheSize & (0x1000 - 1))
#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
#endif
#if CacheSize > 0x8000
/* Enable caching for 32K-64K using fixed MTRR. */
movl $MTRR_FIX_4K_C0000, %ecx
simplemask CacheSize, 0x8000
wrmsr
#endif
#if CacheSize > 0x10000
/* Enable caching for 64K-96K using fixed MTRR. */
movl $MTRR_FIX_4K_D0000, %ecx
simplemask CacheSize, 0x10000
wrmsr
#endif
#if CacheSize > 0x18000
/* Enable caching for 96K-128K using fixed MTRR. */
movl $MTRR_FIX_4K_D8000, %ecx
simplemask CacheSize, 0x18000
wrmsr
#endif
/* Enable caching for 0-32K using fixed MTRR. */
movl $MTRR_FIX_4K_C8000, %ecx
simplemask CacheSize, 0
wrmsr
jmp_if_fam15h(fam15_skip_dram_mtrr_setup)
/* Enable memory access for first MBs using top_mem. */
movl $TOP_MEM, %ecx
xorl %edx, %edx
movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
wrmsr
fam15_skip_dram_mtrr_setup:
#if CONFIG_XIP_ROM_SIZE
/* Enable write base caching so we can do execute in place (XIP)
* on the flash ROM.
*/
movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
*/
movl $_program, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
movl $MTRR_PHYS_MASK(1), %ecx
movl $0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */
jmp_if_k8(wbcache_post_fam10_setup)
movl $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
wbcache_post_fam10_setup:
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE */
/* Set the default memory type and enable fixed and variable MTRRs. */
movl $MTRR_DEF_TYPE_MSR, %ecx
xorl %edx, %edx
movl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax
wrmsr
/* Enable the MTRRs and IORRs in SYSCFG. */
movl $SYSCFG_MSR, %ecx
rdmsr
orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
wrmsr
fam10_mtrr_setup_complete:
post_code(0xa1)
/* Disable conversion of INVD to WBINVD (INVDWBINVD = 0) */
mov $HWCR_MSR, %ecx
rdmsr
btr $4, %eax
wrmsr
jmp_if_not_fam15h(fam15_car_msr_setup_complete)
/* Disable streaming store (DisSS = 1) */
mov $LS_CFG_MSR, %ecx
rdmsr
bts $28, %eax
wrmsr
/* Disable speculative ITLB reloads (DisSpecTlbRld = 1) */
mov $IC_CFG_MSR, %ecx
rdmsr
bts $9, %eax
wrmsr
/* Disable speculative DTLB reloads (DisSpecTlbRld = 1) and set DisHwPf = 1 */
mov $DC_CFG_MSR, %ecx
rdmsr
bts $4, %eax
bts $13, %eax
wrmsr
/* Disable CR0 combining (CombineCr0Cd = 0) */
mov $BU_CFG3_MSR, %ecx
rdmsr
btr $49-32, %edx
wrmsr
fam15_car_msr_setup_complete:
/* Enable cache. */
movl %cr0, %eax
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
movl %eax, %cr0
jmp_if_not_k8(CAR_skip_k8_errata_part1)
/* Set DisFillP on BSP. */
movl $0x8000c068, %eax
movw $0xcf8, %dx
outl %eax, %dx
addw $4, %dx
inl %dx, %eax
bts $10, %eax
outl %eax, %dx
CAR_skip_k8_errata_part1:
jmp_if_k8(fam10_end_part1)
/* So we need to check if it is BSP. */
movl $0x1b, %ecx
rdmsr
bt $8, %eax /* BSP */
jnc CAR_FAM10_ap
fam10_end_part1:
post_code(0xa2)
/* Read the range with lodsl. */
cld
movl $CacheBase, %esi
movl $(CacheSize >> 2), %ecx
rep lodsl
/* Clear the range. */
movl $CacheBase, %edi
movl $(CacheSize >> 2), %ecx
xorl %eax, %eax
rep stosl
jmp_if_not_k8(CAR_skip_k8_errata_part2)
/* Clear DisFillP on BSP. */
movl $0x8000c068, %eax
movw $0xcf8, %dx
outl %eax, %dx
addw $4, %dx
inl %dx, %eax
btr $10, %eax
outl %eax, %dx
CAR_skip_k8_errata_part2:
/* Set up the stack pointer. */
movl $(CacheBase + CacheSize), %eax
movl %eax, %esp
/* Poison the lower stack boundary */
movl $((CacheBase + CacheSize) - CacheSizeBSPStack), %eax
movl $0xdeadbeef, (%eax)
post_code(0xa3)
jmp CAR_FAM10_ap_out
CAR_FAM10_ap:
/*
* Need to set stack pointer for AP.
* It will be from:
* CacheBase + (CacheSize - (CacheSizeBSPStack + CacheSizeBSPSlush))
* - (NodeID << CoreIDbits + CoreID) * CacheSizeAPStack
* The spacing between the BSP stack and the top of the AP
* stacks is purposefully set larger (an extra CacheSizeBSPSlush
* worth of unused space) than necessary to aid debugging when
* additional stack variables are added by future developers.
* The extra space will allow BSP overruns to be caught by
* the warning logic and easily fixed instead of crashing the
* system with no obvious clues of what went wrong.
*
* So, need to get the NodeID and CoreID at first.
* If NB_CFG_MSR bit 54 is set just use initial APIC ID, otherwise need
* to reverse it.
*/
/* Get the coreid bits at first. */
movl $0x80000008, %eax
cpuid
shrl $12, %ecx
andl $0x0f, %ecx
movl %ecx, %edi
/* Get the initial APIC ID. */
movl $1, %eax
cpuid
shrl $24, %ebx
/* Get the nb cfg bit 54. */
movl $NB_CFG_MSR, %ecx
rdmsr
movl %edi, %ecx /* CoreID bits */
bt $(54 - 32), %edx
jc roll_cfg
/* Fam10h NB config bit 54 was not set */
rolb %cl, %bl
roll_cfg:
jmp_if_not_fam15h(ap_apicid_ready)
cmp $0x5, %ecx
jne ap_apicid_ready
/* This is a multi-node CPU
* Adjust the maximum APIC ID to a more reasonable value
* given that no 32-core Family 15h processors exist
*/
movl %ebx, %ecx
and $0x0f, %ecx /* Get lower 4 bits of CPU number */
and $0x60, %ebx /* Get node ID */
shrl $0x1, %ebx /* Shift node ID part of APIC ID down by 1 */
or %ecx, %ebx /* Recombine node ID and CPU number */
ap_apicid_ready:
/* Calculate stack pointer using adjusted APIC ID stored in ebx */
movl $CacheSizeAPStack, %eax
mull %ebx
movl $(CacheBase + (CacheSize - (CacheSizeBSPStack + CacheSizeBSPSlush))), %esp
subl %eax, %esp
/* Restore init detect */
cvtsd2si %xmm5, %ebx
post_code(0xa4)
CAR_FAM10_ap_out:
post_code(0xa5)
/* Disable SSE. */
movl %cr4, %eax
andl $~(3 << 9), %eax
movl %eax, %cr4
post_code(0xa6)
/* Restore the BIST result. */
movl %ebp, %eax
/* We need to set EBP? No need. */
movl %esp, %ebp
pushl %ebx /* Init detected. */
pushl %eax /* BIST */
post_code(0xa7)
call cache_as_ram_main
call post_cache_as_ram
movl %eax, %esp
call cache_as_ram_new_stack
/* We will not go back. */
post_code(0xaf) /* Should never see this POST code. */
all_mtrr_msrs:
/* fixed MTRR MSRs */
.long MTRR_FIX_64K_00000
.long MTRR_FIX_16K_80000
.long MTRR_FIX_16K_A0000
.long MTRR_FIX_4K_C0000
.long MTRR_FIX_4K_C8000
.long MTRR_FIX_4K_D0000
.long MTRR_FIX_4K_D8000
.long MTRR_FIX_4K_E0000
.long MTRR_FIX_4K_E8000
.long MTRR_FIX_4K_F0000
.long MTRR_FIX_4K_F8000
/* var MTRR MSRs */
.long MTRR_PHYS_BASE(0)
.long MTRR_PHYS_MASK(0)
.long MTRR_PHYS_BASE(1)
.long MTRR_PHYS_MASK(1)
.long MTRR_PHYS_BASE(2)
.long MTRR_PHYS_MASK(2)
.long MTRR_PHYS_BASE(3)
.long MTRR_PHYS_MASK(3)
.long MTRR_PHYS_BASE(4)
.long MTRR_PHYS_MASK(4)
.long MTRR_PHYS_BASE(5)
.long MTRR_PHYS_MASK(5)
.long MTRR_PHYS_BASE(6)
.long MTRR_PHYS_MASK(6)
.long MTRR_PHYS_BASE(7)
.long MTRR_PHYS_MASK(7)
/* Variable IORR MTRR MSRs */
.long IORRBase_MSR(0)
.long IORRMask_MSR(0)
.long IORRBase_MSR(1)
.long IORRMask_MSR(1)
/* Top of memory MTRR MSRs */
.long TOP_MEM
.long TOP_MEM2
.long 0x000 /* NULL, end of table */
cache_as_ram_setup_out:

106
src/cpu/amd/car/disable_cache_as_ram.c
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@ -1,106 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* WARNING: this file will be used by both any AP cores and core 0 / node 0
*/
#include <arch/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
static __always_inline uint32_t amd_fam1x_cpu_family(void)
{
uint32_t family;
family = cpuid_eax(0x80000001);
family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
return family;
}
static __always_inline
void disable_cache_as_ram_real(uint8_t skip_sharedc_config)
{
msr_t msr;
uint32_t family;
if (!skip_sharedc_config) {
/* disable cache */
write_cr0(read_cr0() | CR0_CacheDisable);
msr.lo = 0;
msr.hi = 0;
wrmsr(MTRR_FIX_4K_C8000, msr);
if (CONFIG_DCACHE_RAM_SIZE > 0x8000)
wrmsr(MTRR_FIX_4K_C0000, msr);
if (CONFIG_DCACHE_RAM_SIZE > 0x10000)
wrmsr(MTRR_FIX_4K_D0000, msr);
if (CONFIG_DCACHE_RAM_SIZE > 0x18000)
wrmsr(MTRR_FIX_4K_D8000, msr);
/* disable fixed mtrr from now on,
* it will be enabled by ramstage again
*/
msr = rdmsr(SYSCFG_MSR);
msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn
| SYSCFG_MSR_MtrrFixDramModEn);
wrmsr(SYSCFG_MSR, msr);
/* Set the default memory type and
* disable fixed and enable variable MTRRs
*/
msr.hi = 0;
msr.lo = (1 << 11);
wrmsr(MTRR_DEF_TYPE_MSR, msr);
enable_cache();
}
/* INVDWBINVD = 1 */
msr = rdmsr(HWCR_MSR);
msr.lo |= (0x1 << 4);
wrmsr(HWCR_MSR, msr);
family = amd_fam1x_cpu_family();
#if CONFIG(CPU_AMD_MODEL_10XXX)
if (family >= 0x6f) {
/* Family 15h or later */
/* DisSS = 0 */
msr = rdmsr(LS_CFG_MSR);
msr.lo &= ~(0x1 << 28);
wrmsr(LS_CFG_MSR, msr);
if (!skip_sharedc_config) {
/* DisSpecTlbRld = 0 */
msr = rdmsr(IC_CFG_MSR);
msr.lo &= ~(0x1 << 9);
wrmsr(IC_CFG_MSR, msr);
/* Erratum 714: SpecNbReqDis = 0 */
msr = rdmsr(BU_CFG2_MSR);
msr.lo &= ~(0x1 << 8);
wrmsr(BU_CFG2_MSR, msr);
}
/* DisSpecTlbRld = 0 */
/* DisHwPf = 0 */
msr = rdmsr(DC_CFG_MSR);
msr.lo &= ~(0x1 << 4);
msr.lo &= ~(0x1 << 13);
wrmsr(DC_CFG_MSR, msr);
}
#endif
}

135
src/cpu/amd/car/post_cache_as_ram.c
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@ -1,135 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <string.h>
#include <console/console.h>
#include <arch/stages.h>
#include <arch/early_variables.h>
#include <commonlib/helpers.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/car.h>
#include <cpu/amd/msr.h>
#include <arch/acpi.h>
#include <program_loading.h>
#include <romstage_handoff.h>
#include "cpu/amd/car/disable_cache_as_ram.c"
// For set_sysinfo_in_ram()
#include <northbridge/amd/amdfam10/raminit.h>
#if CONFIG_RAMTOP <= 0x100000
#error "You need to set CONFIG_RAMTOP greater than 1M"
#endif
#if CONFIG(DEBUG_CAR)
#define print_car_debug(format, arg...) printk(BIOS_DEBUG, "%s: " format, __func__, ##arg)
#else
#define print_car_debug(format, arg...)
#endif
static void memcpy_(void *d, const void *s, size_t len)
{
print_car_debug(" Copy [%08x-%08x] to [%08x - %08x] ...",
(uint32_t) s, (uint32_t) (s + len - 1),
(uint32_t) d, (uint32_t) (d + len - 1));
memcpy(d, s, len);
}
static int memcmp_(void *d, const void *s, size_t len)
{
print_car_debug(" Compare [%08x-%08x] with [%08x - %08x] ...",
(uint32_t) s, (uint32_t) (s + len - 1),
(uint32_t) d, (uint32_t) (d + len - 1));
return memcmp(d, s, len);
}
/* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33
* and RevGuide for Fam12h, Pub#44739 Rev 3.10
*/
static void vErrata343(void)
{
msr_t msr;
unsigned int uiMask = 0xFFFFFFF7;
msr = rdmsr(BU_CFG2_MSR);
msr.hi &= uiMask; // IcDisSpecTlbWr (bit 35) = 0
wrmsr(BU_CFG2_MSR, msr);
}
asmlinkage void *post_cache_as_ram(void)
{
uint32_t family = amd_fam1x_cpu_family();
int s3resume = 0;
/* Verify that the BSP didn't overrun the lower stack
* boundary during romstage execution
*/
volatile uint32_t *lower_stack_boundary;
lower_stack_boundary = (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) -
CONFIG_DCACHE_BSP_TOP_STACK_SIZE);
if ((*lower_stack_boundary) != 0xdeadbeef)
printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n");
/* ACPI S3 is not supported without RELOCATABLE_RAMSTAGE and
* this will always return 0. */
s3resume = acpi_is_wakeup_s3();
romstage_handoff_init(s3resume);
/* from here don't store more data in CAR */
if (family >= 0x1f && family <= 0x3f) {
/* Family 10h and 12h, 11h until shown otherwise */
vErrata343();
}
size_t car_size = car_data_size();
void *migrated_car = (void *)(CONFIG_RAMTOP - car_size);
print_car_debug("Copying data from cache to RAM...");
memcpy_(migrated_car, _car_global_start, car_size);
print_car_debug(" Done\n");
print_car_debug("Verifying data integrity in RAM...");
if (memcmp_(migrated_car, _car_global_start, car_size) == 0)
print_car_debug(" Done\n");
else
print_car_debug(" FAILED\n");
/* New stack grows right below migrated_car. */
print_car_debug("Switching to use RAM as stack...");
return migrated_car;
}
asmlinkage void cache_as_ram_new_stack(void)
{
print_car_debug("Disabling cache as RAM now\n");
disable_cache_as_ram_real(0); // inline
disable_cache();
/* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */
set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
enable_cache();
set_sysinfo_in_ram(1); // So other core0 could start to train mem
/*copy and execute ramstage */
copy_and_run();
/* We will not return */
print_car_debug("should not be here -\n");
}

90
src/cpu/amd/family_10h-family_15h/Kconfig
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config CPU_AMD_MODEL_10XXX
bool
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SSE2
select TSC_SYNC_LFENCE
select UDELAY_LAPIC
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_MICROCODE_MULTIPLE_FILES
select CAR_GLOBAL_MIGRATION
if CPU_AMD_MODEL_10XXX
config USE_LARGE_DCACHE
bool
default y if CPU_AMD_SOCKET_G34_NON_AGESA
default y if CPU_AMD_SOCKET_FM2_NON_AGESA
default y if CPU_AMD_SOCKET_C32_NON_AGESA
default n
config NUM_IPI_STARTS
int
default 1
config CPU_ADDR_BITS
int
default 48
config DCACHE_RAM_BASE
hex
default 0xc4000
config DCACHE_RAM_SIZE
hex
default 0x0c000
config DCACHE_BSP_TOP_STACK_SIZE
hex
default 0x4000
config DCACHE_BSP_TOP_STACK_SLUSH
hex
default 0x4000 if USE_LARGE_DCACHE
default 0x1000
config DCACHE_AP_STACK_SIZE
hex
default 0x500
config SET_FIDVID
bool
default y
config MAX_PHYSICAL_CPUS
int
default 1
config LIFT_BSP_APIC_ID
bool
default n
if SET_FIDVID
config SET_FIDVID_DEBUG
bool
default y
config SET_FIDVID_STORE_AP_APICID_AT_FIRST
bool
default y
config SET_FIDVID_CORE0_ONLY
bool
default n
# 0: all cores
# 1: core 0 only
# 2: all but core 0
config SET_FIDVID_CORE_RANGE
int
default 0
endif # SET_FIDVID
config UDELAY_LAPIC_FIXED_FSB
int
default 200
endif # CPU_AMD_MODEL_10XXX

25
src/cpu/amd/family_10h-family_15h/Makefile.inc
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romstage-y += ../../x86/mtrr/earlymtrr.c
romstage-y += ../car/post_cache_as_ram.c
romstage-y += init_cpus.c
ramstage-y += model_10xxx_init.c
ramstage-y += processor_name.c
romstage-y += update_microcode.c
romstage-y += tsc_freq.c
ramstage-y += tsc_freq.c
romstage-y += ram_calc.c
ramstage-y += ram_calc.c
ramstage-y += monotonic_timer.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
# Microcode for Family 10h, 11h, 12h, and 14h
cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd.bin
microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin
microcode_amd.bin-type := microcode
# Microcode for Family 15h
cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd_fam15h.bin
microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin
microcode_amd_fam15h.bin-type := microcode

834
src/cpu/amd/family_10h-family_15h/defaults.h
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/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <northbridge/amd/amdmct/amddefs.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/msr.h>
/*
* Default MSR and errata settings.
*/
static const struct {
u32 msr;
uint64_t revision;
u32 platform;
u32 data_lo;
u32 data_hi;
u32 mask_lo;
u32 mask_hi;
} fam10_msr_default[] = {
{ TOP_MEM2, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF },
{ SYSCFG_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
3 << 21, 0x00000000,
3 << 21, 0x00000000 }, /* [MtrrTom2En]=1,[TOM2EnWB] = 1*/
{ MC1_CTL_MASK, AMD_OR_B2, AMD_PTYPE_ALL,
1 << 18, 0x00000000,
1 << 18, 0x00000000 }, /* Erratum 586: [DEIBP]=1 */
{ MC1_CTL_MASK, AMD_OR_B2, AMD_PTYPE_ALL,
1 << 15, 0x00000000,
1 << 15, 0x00000000 }, /* Erratum 593: [BSRP]=1 */
{ MC1_CTL_MASK, AMD_OR_C0, AMD_PTYPE_ALL,
1 << 15, 0x00000000,
1 << 15, 0x00000000 }, /* Erratum 739: [BSRP]=1 */
{ 0xc0011000, AMD_FAM15_ALL, AMD_PTYPE_ALL,
1 << 16, 0x00000000,
1 << 16, 0x00000000 }, /* Erratum 608: [bit 16]=1 */
{ 0xc0011000, AMD_OR_C0, AMD_PTYPE_ALL,
1 << 15, 0x00000000,
1 << 15, 0x00000000 }, /* Erratum 727: [bit 15]=1 */
{ MC4_CTL_MASK, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
0xF << 19, 0x00000000,
0xF << 19, 0x00000000 }, /* [RtryHt[0..3]]=1 */
{ MC4_CTL_MASK, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
1 << 10, 0x00000000,
1 << 10, 0x00000000 }, /* [GartTblWkEn]=1 */
{ DC_CFG_MSR, AMD_FAM10_ALL, AMD_PTYPE_SVR,
0x00000000, 0x00000004,
0x00000000, 0x0000000C }, /* Family 10h: [REQ_CTR] = 1 for Server */
{ DC_CFG_MSR, AMD_DR_Bx, AMD_PTYPE_SVR,
0x00000000, 0x00000000,
0x00000000, 0x00000C00 }, /* Erratum 326 */
{ NB_CFG_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC,
0x00000000, 1 << 22,
0x00000000, 1 << 22 }, /* [ApicInitIDLo]=1 */
{ NB_CFG_MSR, AMD_FAM15_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC,
1 << 23, 0x00000000,
1 << 23, 0x00000000 }, /* Erratum 663: [bit 23]=1 */
{ BU_CFG2_MSR, AMD_DR_Bx, AMD_PTYPE_ALL,
1 << 29, 0x00000000,
1 << 29, 0x00000000 }, /* For Bx Smash1GPages=1 */
{ DC_CFG_MSR, AMD_FAM10_ALL, AMD_PTYPE_ALL,
1 << 24, 0x00000000,
1 << 24, 0x00000000 }, /* Erratum #261 [DIS_PIGGY_BACK_SCRUB]=1 */
{ LS_CFG_MSR, AMD_DR_GT_B0, AMD_PTYPE_ALL,
0 << 1, 0x00000000,
1 << 1, 0x00000000 }, /* IDX_MATCH_ALL=0 */
{ IC_CFG_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
0x00000000, 1 << (39-32),
0x00000000, 1 << (39-32)}, /* C0 or above [DisLoopPredictor]=1 */
{ IC_CFG_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
0xf << 1, 0x00000000,
0xf << 1, 0x00000000}, /* C0 or above [DisIcWayFilter]=0xf */
{ BU_CFG_MSR, AMD_DR_LT_B3, AMD_PTYPE_ALL,
1 << 21, 0x00000000,
1 << 21, 0x00000000 }, /* Erratum #254 DR B1 BU_CFG_MSR[21]=1 */
{ BU_CFG_MSR, AMD_DR_LT_B3, AMD_PTYPE_ALL,
1 << 23, 0x00000000,
1 << 23, 0x00000000 }, /* Erratum #309 BU_CFG_MSR[23]=1 */
{ BU_CFG_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0 << 10, 0x00000000,
1 << 10, 0x00000000 }, /* [DcacheAgressivePriority]=0 */
/* CPUID_EXT_FEATURES */
{ CPU_ID_FEATURES_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC,
1 << 28, 0x00000000,
1 << 28, 0x00000000 }, /* [HyperThreadFeatEn]=1 */
{ CPU_ID_FEATURES_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC,
0x00000000, 1 << (33-32),
0x00000000, 1 << (33-32) }, /* [ExtendedFeatEn]=1 */
{ DE_CFG_MSR, AMD_OR_B2, AMD_PTYPE_ALL,
1 << 10, 0x00000000,
1 << 10, 0x00000000 }, /* Bx [ResyncPredSingleDispDis]=1 */
{ BU_CFG2_MSR, AMD_DRBH_Cx, AMD_PTYPE_ALL,
0x00000000, 1 << (35-32),
0x00000000, 1 << (35-32) }, /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() ) */
{ BU_CFG3_MSR, AMD_OR_B2, AMD_PTYPE_ALL,
0x00000000, 1 << (42-32),
0x00000000, 1 << (42-32)}, /* Bx [PwcDisableWalkerSharing]=1 */
{ BU_CFG3_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
1 << 22, 0x00000000,
1 << 22, 0x00000000}, /* C0 or above [PfcDoubleStride]=1 */
{ EX_CFG_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
0x00000000, 1 << (54-32),
0x00000000, 1 << (54-32)}, /* C0 or above [LateSbzResync]=1 */
{ LS_CFG2_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
1 << 23, 0x00000000,
1 << 23, 0x00000000}, /* C0 or above [DisScbThreshold]=1 */
{ LS_CFG2_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
1 << 14, 0x00000000,
1 << 14, 0x00000000}, /* C0 or above [ForceSmcCheckFlowStDis]=1 */
{ LS_CFG2_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
1 << 12, 0x00000000,
1 << 12, 0x00000000}, /* C0 or above [ForceBusLockDis]=1 */
{ OSVW_ID_Length, AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL,
0x00000004, 0x00000000,
0x00000004, 0x00000000}, /* B0 or Above, OSVW_ID_Length is 0004h */
{ OSVW_Status, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_MC,
0x0000000C, 0x00000000,
0x0000000C, 0x00000000}, /* Cx and Dx multiple-link processor */
{ OSVW_ID_Length, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000005, 0x00000000,
0x0000ffff, 0x00000000}, /* OSVW_ID_Length = 0x5 */
{ OSVW_Status, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000010, 0x00000000,
0xffffffff, 0x00000000}, /* OsvwId4 = 0x1 */
{ BU_CFG2_MSR, AMD_DR_Dx, AMD_PTYPE_ALL,
0x00000000, 1 << (50-32),
0x00000000, 1 << (50-32)}, /* D0 or Above, RdMmExtCfgQwEn*/
{ BU_CFG2_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000000, 0x0 << (36-32),
0x00000000, 0x3 << (36-32)}, /* [ThrottleNbInterface]=0 */
{ BU_CFG2_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
1 << 10, 0x00000000,
1 << 10, 0x00000000}, /* [VicResyncChkEn]=1 */
{ BU_CFG2_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
1 << 11, 0x00000000,
1 << 11, 0x00000000}, /* Erratum 503: [bit 11]=1 */
{ CPU_ID_EXT_FEATURES_MSR, AMD_DR_Dx, AMD_PTYPE_ALL,
0x00000000, 1 << (51 - 32),
0x00000000, 1 << (51 - 32)}, /* G34_PKG | C32_PKG | S1G4_PKG | ASB2_PKG */
{ CPU_ID_EXT_FEATURES_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000000, 1 << (56 - 32),
0x00000000, 1 << (56 - 32)}, /* [PerfCtrExtNB]=1 */
{ CPU_ID_EXT_FEATURES_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000000, 1 << (55 - 32),
0x00000000, 1 << (55 - 32)}, /* [PerfCtrExtCore]=1 */
{ IBS_OP_DATA3_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0 << 16, 0x00000000,
1 << 16, 0x00000000}, /* [IbsDcMabHit]=0 */
{ MC4_MISC0, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000000, 0x1 << (52-32),
0x00000000, 0xf << (52-32)}, /* [LvtOffset]=1 */
{ MC4_MISC1, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000000, 0x1 << (52-32),
0x00000000, 0xf << (52-32)}, /* [LvtOffset]=1 */
{ MC4_MISC2, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000000, 0x1 << (52-32),
0x00000000, 0xf << (52-32)}, /* [LvtOffset]=1 */
};
/*
* Default PCI and errata settings.
*/
static const struct {
u8 function;
u16 offset;
uint64_t revision;
u32 platform;
u32 data;
u32 mask;
} fam10_pci_default[] = {
/* Function 0 - HT Config */
{ 0, 0x68, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
0x000e0000, 0x000e0000 }, /* [19:17] for 8bit APIC config */
{ 0, 0x68, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
0x00400000, 0x00600000 }, /* [22:21] DsNpReqLmt = 10b */
{ 0, 0x68, AMD_FAM10_LT_D, AMD_PTYPE_ALL,
0x00004000, 0x00006000 }, /* [14:13] BufRelPri = 2h */
{ 0, 0x68, (AMD_FAM10_REV_D | AMD_FAM15_ALL), AMD_PTYPE_ALL,
0x00002000, 0x00006000 }, /* [14:13] BufRelPri = 1h */
{ 0, 0x68, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
0x00000800, 0x00000800 }, /* [11] RspPassPW = 1 */
/* Errata 281 Workaround */
{ 0, 0x68, (AMD_DR_B0 | AMD_DR_B1),
AMD_PTYPE_SVR, 0x00200000, 0x00600000 }, /* [22:21] DsNpReqLmt0 = 01b */
{ 0, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
{ 0, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
{ 0, 0xC4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
{ 0, 0xE4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
/* Link Global Retry Control Register */
{ 0, 0x150, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
0x00073900, 0x00073f70 }, /* TotalRetryAttempts = 0x7,
HtRetryCrcDatInsDynEn = 0x1,
HtRetryCrcCmdPackDynEn = 0x1,
HtRetryCrcDatIns = 0x4,
HtRetryCrcCmdPack = 0x1,
ForceErrType = 0x0,
MultRetryErr = 0x0 */
/* Errata 600 */
{ 0, 0x150, AMD_OR_B2, AMD_PTYPE_ALL,
0x00000000, 0x00000e00 }, /* HtRetryCrcDatIns = 0x0 */
/* Errata 351
* System software should program the Link Extended Control Registers[LS2En]
* (F0x[18C:170][8]) to 0b for all links. System software should also
* program Link Global Extended Control Register[ForceFullT0]
* (F0x16C[15:13]) to 000b */
{ 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, /* Fix FAM10_ALL when fixed in rev guide */
0x00000000, 0x00000100 },
{ 0, 0x174, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0x00000000, 0x00000100 },
{ 0, 0x178, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0x00000000, 0x00000100 },
{ 0, 0x17C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0x00000000, 0x00000100 },
{ 0, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0x00000000, 0x00000100 },
{ 0, 0x184, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0x00000000, 0x00000100 },
{ 0, 0x188, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0x00000000, 0x00000100 },
{ 0, 0x18C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0x00000000, 0x00000100 },
/* Link Global Extended Control Register */
{ 0, 0x16C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0x00000014, 0x0000003F }, /* [15:13] ForceFullT0 = 0b,
* Set T0Time 14h per BKDG */
{ 0, 0x170, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000100, 0x00000100 },
{ 0, 0x174, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000100, 0x00000100 },
{ 0, 0x178, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000100, 0x00000100 },
{ 0, 0x17C, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000100, 0x00000100 },
{ 0, 0x180, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000100, 0x00000100 },
{ 0, 0x184, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000100, 0x00000100 },
{ 0, 0x188, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000100, 0x00000100 },
{ 0, 0x18C, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000100, 0x00000100 },
/* Link Global Extended Control Register */
{ 0, 0x16C, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000014, 0x0000003F }, /* [15:13] ForceFullT0 = 111b,
* Set T0Time 26h per BKDG */
{ 0, 0x16C, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x7 << 13, 0x7 << 13 }, /* [15:13] ForceFullT0 = 7h */
{ 0, 0x16C, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x26, 0x3f }, /* [5:0] T0Time = 26h */
/* Function 1 - Map Init */
/* Before reading F1x114_x2 or F1x114_x3 software must
* initialize the registers or NB Array MCA errors may
* occur. BIOS should initialize index 0h of F1x114_x2 and
* F1x114_x3 to prevent reads from F1x114 from generating NB
* Array MCA errors. BKDG Doc #3116 Rev 1.07
*/
{ 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0x20000000, 0xFFFFFFFF }, /* Select extended MMIO Base */
{ 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0x00000000, 0xFFFFFFFF }, /* Clear map */
{ 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0x30000000, 0xFFFFFFFF }, /* Select extended MMIO Base */
{ 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0x00000000, 0xFFFFFFFF }, /* Clear map */
/* Function 2 - DRAM Controller */
/* Function 3 - Misc. Control */
{ 3, 0x40, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
0x00000100, 0x00000100 }, /* [8] MstrAbrtEn */
{ 3, 0x44, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
0x4A30005C, 0x4A30005C }, /* [30] SyncOnDramAdrParErrEn = 1,
[27] NbMcaToMstCpuEn = 1,
[25] DisPciCfgCpuErrRsp = 1,
[21] SyncOnAnyErrEn = 1,
[20] SyncOnWDTEn = 1,
[6] CpuErrDis = 1,
[4] SyncPktPropDis = 1,
[3] SyncPktGenDis = 1,
[2] SyncOnUcEccEn = 1 */
/* XBAR buffer settings */
{ 3, 0x6c, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL,
0x00018052, 0x700780f7 }, /* IsocRspDBC = 0x0,
UpRspDBC = 0x1,
DatBuf24 = 0x1,
DnRspDBC = 0x1,
DnReqDBC = 0x1,
UpReqDBC = 0x2 */
/* XBAR buffer settings */
{ 3, 0x6c, AMD_DR_Dx, AMD_PTYPE_ALL,
0x00028052, 0x700780f7 }, /* IsocRspDBC = 0x0,
UpRspDBC = 0x2,
DatBuf24 = 0x1,
DnRspDBC = 0x1,
DnReqDBC = 0x1,
UpReqDBC = 0x2 */
/* XBAR buffer settings */
{ 3, 0x6c, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x10010052, 0x700700f7 }, /* IsocRspDBC = 0x1,
UpRspDBC = 0x1,
DnRspDBC = 0x1,
DnReqDBC = 0x1,
UpReqDBC = 0x2 */
/* Errata 281 Workaround */
{ 3, 0x6c, (AMD_DR_B0 | AMD_DR_B1),
AMD_PTYPE_SVR, 0x00010094, 0x700780F7 },
{ 3, 0x6c, AMD_FAM10_ALL, AMD_PTYPE_UMA,
0x60018051, 0x700780F7 },
{ 3, 0x70, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL,
0x00041153, 0x777777f7 }, /* IsocRspCBC = 0x0,
IsocPreqCBC = 0x0,
IsocReqCBC = 0x0,
UpRspCBC = 0x4,
DnPreqCBC = 0x1,
UpPreqCBC = 0x1,
DnRspCBC = 0x1,
DnReqCBC = 0x1,
UpReqCBC = 0x3 */
{ 3, 0x70, AMD_DR_Dx, AMD_PTYPE_ALL,
0x00051153, 0x777777f7 }, /* IsocRspCBC = 0x0,
IsocPreqCBC = 0x0,
IsocReqCBC = 0x0,
UpRspCBC = 0x5,
DnPreqCBC = 0x1,
UpPreqCBC = 0x1,
DnRspCBC = 0x1,
DnReqCBC = 0x1,
UpReqCBC = 0x3 */
{ 3, 0x70, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x10171155, 0x777777f7 }, /* IsocRspCBC = 0x1,
IsocPreqCBC = 0x0,
IsocReqCBC = 0x1,
UpRspCBC = 0x7,
DnPreqCBC = 0x1,
UpPreqCBC = 0x1,
DnRspCBC = 0x1,
DnReqCBC = 0x1,
UpReqCBC = 0x5 */
{ 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_UMA,
0x61221151, 0x777777f7 }, /* IsocRspCBC = 0x6,
IsocPreqCBC = 0x1,
IsocReqCBC = 0x2,
UpRspCBC = 0x2,
DnPreqCBC = 0x1,
UpPreqCBC = 0x1,
DnRspCBC = 0x1,
DnReqCBC = 0x1,
UpReqCBC = 0x1 */
{ 3, 0x74, AMD_FAM10_ALL, ~AMD_PTYPE_UMA,
0x00081111, 0xf7ff7777 }, /* DRReqCBC = 0x0,
IsocPreqCBC = 0x0,
IsocReqCBC = 0x0,
ProbeCBC = 0x8,
DnPreqCBC = 0x1,
UpPreqCBC = 0x1,
DnReqCBC = 0x1,
UpReqCBC = 0x1 */
{ 3, 0x74, AMD_FAM10_ALL, AMD_PTYPE_UMA,
0x00480101, 0xf7ff7777 }, /* DRReqCBC = 0x0,
IsocPreqCBC = 0x0,
IsocReqCBC = 0x4,
ProbeCBC = 0x8,
DnPreqCBC = 0x0,
UpPreqCBC = 0x1,
DnReqCBC = 0x0,
UpReqCBC = 0x1 */
{ 3, 0x74, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00172111, 0xf7ff7777 }, /* DRReqCBC = 0x0,
IsocPreqCBC = 0x0,
IsocReqCBC = 0x1,
ProbeCBC = 0x7,
DnPreqCBC = 0x2,
UpPreqCBC = 0x1,
DnReqCBC = 0x1,
UpReqCBC = 0x1 */
{ 3, 0x7c, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL,
0x00090914, 0x707fff1f }, /* XBar2SriFreeListCBInc = 0x0,
Sri2XbarFreeRspDBC = 0x0,
Sri2XbarFreeXreqDBC = 0x9,
Sri2XbarFreeRspCBC = 0x0,
Sri2XbarFreeXreqCBC = 0x9,
Xbar2SriFreeListCBC = 0x14 */
{ 3, 0x7c, AMD_DR_Dx, AMD_PTYPE_ALL,
0x00090a18, 0x707fff1f }, /* XBar2SriFreeListCBInc = 0x0,
Sri2XbarFreeRspDBC = 0x0,
Sri2XbarFreeXreqDBC = 0x9,
Sri2XbarFreeRspCBC = 0x0,
Sri2XbarFreeXreqCBC = 0x9,
Xbar2SriFreeListCBC = 0x14 */
/* Errata 281 Workaround */
{ 3, 0x7C, ( AMD_DR_B0 | AMD_DR_B1),
AMD_PTYPE_SVR, 0x00144514, 0x707FFF1F },
{ 3, 0x7c, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x040d0f16, 0x77ffff1f }, /* XBar2SriFreeListCBInc = 0x0,
SrqExtFreeListBC = 0x8,
Sri2XbarFreeRspDBC = 0x0,
Sri2XbarFreeXreqDBC = 0xd,
Sri2XbarFreeRspCBC = 0x0,
Sri2XbarFreeXreqCBC = 0xf,
Xbar2SriFreeListCBC = 0x16 */
{ 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_UMA,
0x00070814, 0x007FFF1F },
{ 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0x00800756, 0x00F3FFFF },
{ 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_UMA,
0x00C37756, 0x00F3FFFF },
{ 3, 0x144, AMD_FAM10_ALL, AMD_PTYPE_UMA,
0x00000036, 0x000000FF },
{ 3, 0x140, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00a11755, 0x00f3ffff },
/* Errata 281 Workaround */
{ 3, 0x144, ( AMD_DR_B0 | AMD_DR_B1),
AMD_PTYPE_SVR, 0x00000001, 0x0000000F },
/* [3:0] RspTok = 0001b */
{ 3, 0x144, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000028, 0x000000ff },
{ 3, 0x148, AMD_FAM10_ALL, AMD_PTYPE_UMA,
0x8000052A, 0xD5FFFFFF },
/* Core Interface Buffer Count */
{ 3, 0x1a0, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00034004, 0x00037007 }, /* CpuToNbFreeBufCnt = 0x3,
L3ToSriReqCBC = 0x4,
L3FreeListCBC = default,
CpuCmdBufCnt = 0x4 */
/* ACPI Power State Control Reg1 */
{ 3, 0x80, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0xE6002200, 0xFFFFFFFF },
/* ACPI Power State Control Reg1 */
{ 3, 0x80, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0xe20be200, 0xefefef00 },
/* ACPI Power State Control Reg2 */
{ 3, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0xA0E641E6, 0xFFFFFFFF },
/* ACPI Power State Control Reg2 */
{ 3, 0x84, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x01e200e2, 0xefef00ef },
{ 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_MOB | AMD_PTYPE_DSK,
0x00000080, 0x00000080 }, /* [7] PSIVidEnable */
{ 3, 0xA0, AMD_DR_Bx, AMD_PTYPE_ALL,
0x00002800, 0x000003800 }, /* [13:11] PllLockTime = 5 */
{ 3, 0xA0, ((AMD_FAM10_ALL | AMD_FAM15_ALL) & ~(AMD_DR_Bx)), AMD_PTYPE_ALL,
0x00000800, 0x000003800 }, /* [13:11] PllLockTime = 1 */
/* Reported Temp Control Register */
{ 3, 0xA4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
0x00000080, 0x00000080 }, /* [7] TempSlewDnEn = 1 */
/* Clock Power/Timing Control 0 Register */
{ 3, 0xD4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
0xC0000F00, 0xF0000F00 }, /* [31] NbClkDivApplyAll = 1,
[30:28] NbClkDiv = 100b,[11:8] ClkRampHystSel = 1111b */
/* Clock Power/Timing Control 1 Register */
{ 3, 0xD8, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
0x03000010, 0x0F000070 }, /* [6:4] VSRampTime = 1,
* [27:24] ReConDel = 3 */
/* Clock Power/Timing Control 1 Register */
{ 3, 0xD8, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0x00000006, 0x00000007 }, /* [2:0] VSSlamTime = 6 */
/* Clock Power/Timing Control 2 Register */
{ 3, 0xDC, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
0x00005000, 0x00007000 }, /* [14:12] NbsynPtrAdj = 5 */
/* Extended NB MCA Config Register */
{ 3, 0x180, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
0x007003E2, 0x007003E2 }, /* [22:20] = SyncFloodOn_Err = 7,
[9] SyncOnUncNbAryEn = 1 ,
[8] SyncOnProtEn = 1,
[7] SyncFloodOnTgtAbtErr = 1,
[6] SyncFloodOnDatErr = 1,
[5] DisPciCfgCpuMstAbtRsp = 1,
[1] SyncFloodOnUsPwDataErr = 1 */
/* NB Configuration 2 */
{ 3, 0x188, AMD_DR_GT_B0, AMD_PTYPE_ALL,
0x00000010, 0x00000010 }, /* EnStpGntOnFlushMaskWakeup = 0x1 */
/* NB Configuration 2 */
{ 3, 0x188, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000200, 0x00000200 }, /* DisL3HiPriFreeListAlloc = 0x1 */
/* errata 346 - Fam10 C2, C3
* System software should set F3x188[22] to 1b. */
{ 3, 0x188, AMD_DR_Cx, AMD_PTYPE_ALL,
0x00400000, 0x00400000 },
/* L3 Control Register */
{ 3, 0x1b8, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
0x00001000, 0x00001000 }, /* [12] = L3PrivReplEn */
/* Errata 504 workaround */
{ 3, 0x1b8, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00040000, 0x00040000 }, /* [18] = 1b */
/* IBS Control Register */
{ 3, 0x1cc, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
0x00000100, 0x00000100 }, /* [8] = LvtOffsetVal */
/* Erratum 619 - Family 15h Bx
* System software should set F5x88[14] to 1b. */
{ 5, 0x88, AMD_OR_B2, AMD_PTYPE_ALL,
1 << 14, 1 << 14 },
/* L3 Control 2 */
{ 3, 0x1b8, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000090, 0x000001d0 }, /* ImplRdProjDelayThresh = 0x2,
ImplRdAnySubUnavail = 0x1 */
};
/*
* Default HyperTransport Phy and errata settings.
*/
static const struct {
u16 htreg; /* HT Phy Register index */
uint64_t revision;
u32 platform;
u32 linktype;
u32 data;
u32 mask;
} fam10_htphy_default[] = {
/* Errata 344 - Fam10 C2/C3, D0/D1
* System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */
{ 0x60, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x61, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x62, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x63, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x64, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x65, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x66, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x67, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x68, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x70, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x71, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x72, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x73, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x74, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x75, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x76, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x77, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x78, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
/* Errata 354 - Fam10 C2, C3
* System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */
{ 0x40, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x41, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x42, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x43, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x44, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x45, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x46, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x47, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x48, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x50, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x51, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x52, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x53, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x54, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x55, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x56, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x57, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
{ 0x58, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 },
/* Errata 327 - Fam10 C2/C3, D0/D1
* BIOS should set the Link Phy Impedance Register[RttCtl]
* (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and
* Link Phy Impedance Register[RttIndex]
* (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */
{ 0xC0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x40040000, 0xe01F0000 },
{ 0xD0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x40040000, 0xe01F0000 },
{ 0x520A,AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */
{ 0x530A, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */
{ 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */
{ 0x530A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */
{ 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
0x0000005a, 0x000000ff }, /* Use common "safe" setting for K10 */
{ 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
0x0000005a, 0x000000ff }, /* Use common "safe" setting for K10 */
{ 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
{ 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
/* Link Phy Receiver Loop Filter Registers */
{ 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h,
[21:14] LfcMin = 10h */
{ 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h,
[21:14] LfcMin = 10h */
{ 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h,
[21:14] LfcMin = 08h */
{ 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h,
[21:14] LfcMin = 08h */
{ 0xC0, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h,
[20:16] RttIndex = 04h */
{ 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa,
P0XmtRdPtr = 0x2
P1RcvRdPtr = 0xa
P1XmtRdPtr = 0x0 */
{ 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa,
P0XmtRdPtr = 0x2
P1RcvRdPtr = 0xa
P1XmtRdPtr = 0x0 */
{ 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd,
P0XmtRdPtr = 0x4
P1RcvRdPtr = 0xd
P1XmtRdPtr = 0x0 */
{ 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd,
P0XmtRdPtr = 0x4
P1RcvRdPtr = 0xd
P1XmtRdPtr = 0x0 */
/* Link Phy Receiver Loop Filter Registers */
{ 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h,
[21:14] LfcMin = 10h */
{ 0xC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h,
[21:14] LfcMin = 10h */
{ 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h,
[21:14] LfcMin = 08h */
{ 0xC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h,
[21:14] LfcMin = 08h */
{ 0xC0, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h,
[20:16] RttIndex = 04h */
{ 0xc4, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
0x00013480, 0x0003fc80 }, /* [17:10] DCV = 0x4d,
[7] DfeEn = 0x1 */
{ 0xd4, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
0x00013480, 0x0003fc80 }, /* [17:10] DCV = 0x4d,
[7] DfeEn = 0x1 */
};

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src/cpu/amd/family_10h-family_15h/fidvid.c
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1849
src/cpu/amd/family_10h-family_15h/init_cpus.c
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/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef INIT_CPUS_H
#define INIT_CPUS_H
#include <cpu/x86/lapic.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
#include <cpu/amd/multicore.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include "defaults.h"
#define NODE_HT(x) NODE_PCI(x,0)
#define NODE_MP(x) NODE_PCI(x,1)
#define NODE_MC(x) NODE_PCI(x,3)
#define NODE_LC(x) NODE_PCI(x,4)
unsigned int get_sbdn(unsigned int bus);
void cpuSetAMDMSR(uint8_t node_id);
typedef void (*process_ap_t) (u32 apicid, void *gp);
uint32_t get_boot_apic_id(uint8_t node, uint32_t core);
u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo);
uint8_t set_apicid_cpuid_lo(void);
void real_start_other_core(uint32_t nodeid, uint32_t cores);
void finalize_node_setup(struct sys_info *sysinfo);
uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2);
void start_other_cores(uint32_t bsp_apicid);
u32 get_core_num_in_bsp(u32 nodeid);
void update_microcode(u32 cpu_deviceid);
/* fidvid.c */
void init_fidvid_stage2(u32 apicid, u32 nodeid);
void prep_fid_change(void);
int init_fidvid_bsp(u32 bsp_apicid, u32 nodes);
#endif

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/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <cpu/x86/smm.h>
#include <cpu/x86/pae.h>
#include <cpu/x86/lapic.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/amd/multicore.h>
static inline uint8_t is_gt_rev_d(void)
{
uint8_t fam15h = 0;
uint8_t rev_gte_d = 0;
uint32_t family;
uint32_t model;
family = model = cpuid_eax(0x80000001);
model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4);
family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
if (family >= 0x6f)
/* Family 15h or later */
fam15h = 1;
if ((model >= 0x8) || fam15h)
/* Revision D or later */
rev_gte_d = 1;
return rev_gte_d;
}
static volatile uint8_t fam15h_startup_flags[MAX_NODES_SUPPORTED][MAX_CORES_SUPPORTED] = {{ 0 }};
static void model_10xxx_init(struct device *dev)
{
u8 i;
msr_t msr;
int num_banks;
struct node_core_id id;
#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif
uint8_t delay_start;
id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
if (is_fam15h())
delay_start = !!(id.coreid & 0x1);
else
delay_start = 0;
/* Turn on caching if we haven't already */
x86_enable_cache();
if (!delay_start) {
/* Initialize all variable MTRRs except the first pair.
* This prevents Linux from having to correct an inconsistent
* MTRR setup, which would crash Family 15h CPUs due to the
* compute unit structure sharing MTRR MSRs between AP cores.
*/
msr.hi = 0x00000000;
msr.lo = 0x00000000;
disable_cache();
for (i = 0x2; i < 0x10; i++) {
wrmsr(MTRR_PHYS_BASE(0) | i, msr);
}
enable_cache();
/* Set up other MTRRs */
amd_setup_mtrrs();
} else {
while (!fam15h_startup_flags[id.nodeid][id.coreid - 1]) {
/* Wait for CU first core startup */
}
}
x86_mtrr_check();
disable_cache();
/* zero the machine check error status registers */
msr = rdmsr(IA32_MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < num_banks; i++)
wrmsr(IA32_MC0_STATUS + (i * 4), msr);
enable_cache();
/* Enable the local CPU APICs */
setup_lapic();
/* Set the processor name string */
init_processor_name();
#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
msr.lo |= 1 << 28;
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |= 1 << (33 - 32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
#endif
/* Set bus unit configuration */
if (is_fam15h()) {
uint32_t f5x80;
uint8_t enabled;
uint8_t compute_unit_count = 0;
f5x80 = pci_read_config32(pcidev_on_root(0x18 + id.nodeid, 5),
0x80);
enabled = f5x80 & 0xf;
if (enabled == 0x1)
compute_unit_count = 1;
if (enabled == 0x3)
compute_unit_count = 2;
if (enabled == 0x7)
compute_unit_count = 3;
if (enabled == 0xf)
compute_unit_count = 4;
msr = rdmsr(BU_CFG2_MSR);
msr.lo &= ~(0x3 << 6); /* ThrottleNbInterface[1:0] */
msr.lo |= (((compute_unit_count - 1) & 0x3) << 6);
wrmsr(BU_CFG2_MSR, msr);
} else {
uint32_t f0x60;
uint32_t f0x160;
uint8_t core_count = 0;
uint8_t node_count = 0;
f0x60 = pci_read_config32(pcidev_on_root(0x18 + id.nodeid, 0),
0x60);
core_count = (f0x60 >> 16) & 0x1f;
node_count = ((f0x60 >> 4) & 0x7) + 1;
if (is_gt_rev_d()) {
f0x160 = pci_read_config32(
pcidev_on_root(0x18 + id.nodeid, 0), 0x160);
core_count |= ((f0x160 >> 16) & 0x7) << 5;
}
core_count++;
core_count /= node_count;
msr = rdmsr(BU_CFG2_MSR);
if (is_gt_rev_d()) {
msr.hi &= ~(0x3 << (36 - 32)); /* ThrottleNbInterface[3:2] */
msr.hi |= ((((core_count - 1) >> 2) & 0x3) << (36 - 32));
}
msr.lo &= ~(0x3 << 6); /* ThrottleNbInterface[1:0] */
msr.lo |= (((core_count - 1) & 0x3) << 6);
msr.lo &= ~(0x1 << 24); /* WcPlusDis = 0 */
wrmsr(BU_CFG2_MSR, msr);
}
/* Disable Cf8ExtCfg */
msr = rdmsr(NB_CFG_MSR);
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
if (is_fam15h()) {
msr = rdmsr(BU_CFG3_MSR);
/* Set CombineCr0Cd */
msr.hi |= (1 << (49-32));
wrmsr(BU_CFG3_MSR, msr);
} else {
msr = rdmsr(BU_CFG2_MSR);
/* Clear ClLinesToNbDis */
msr.lo &= ~(1 << 15);
/* Clear bit 35 as per Erratum 343 */
msr.hi &= ~(1 << (35-32));
wrmsr(BU_CFG2_MSR, msr);
}
if (CONFIG(HAVE_SMI_HANDLER)) {
printk(BIOS_DEBUG, "Initializing SMM ASeg memory\n");
/* Set SMM base address for this CPU */
msr = rdmsr(SMM_BASE_MSR);
msr.lo = SMM_BASE - (lapicid() * 0x400);
wrmsr(SMM_BASE_MSR, msr);
/* Enable the SMM memory window */
msr = rdmsr(SMM_MASK_MSR);
msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
wrmsr(SMM_MASK_MSR, msr);
} else {
printk(BIOS_DEBUG, "Disabling SMM ASeg memory\n");
/* Set SMM base address for this CPU */
msr = rdmsr(SMM_BASE_MSR);
msr.lo = SMM_BASE - (lapicid() * 0x400);
wrmsr(SMM_BASE_MSR, msr);
/* Disable the SMM memory window */
msr.hi = 0x0;
msr.lo = 0x0;
wrmsr(SMM_MASK_MSR, msr);
}
/* Set SMMLOCK to avoid exploits messing with SMM */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);
wrmsr(HWCR_MSR, msr);
fam15h_startup_flags[id.nodeid][id.coreid] = 1;
}
static struct device_operations cpu_dev_ops = {
.init = model_10xxx_init,
};
static const struct cpu_device_id cpu_table[] = {
//AMD_GH_SUPPORT
{ X86_VENDOR_AMD, 0x100f00 }, /* SH-F0 L1 */
{ X86_VENDOR_AMD, 0x100f10 }, /* M2 */
{ X86_VENDOR_AMD, 0x100f20 }, /* S1g1 */
{ X86_VENDOR_AMD, 0x100f21 },
{ X86_VENDOR_AMD, 0x100f2A },
{ X86_VENDOR_AMD, 0x100f22 },
{ X86_VENDOR_AMD, 0x100f23 },
{ X86_VENDOR_AMD, 0x100f40 }, /* RB-C0 */
{ X86_VENDOR_AMD, 0x100f42 }, /* RB-C2 */
{ X86_VENDOR_AMD, 0x100f43 }, /* RB-C3 */
{ X86_VENDOR_AMD, 0x100f52 }, /* BL-C2 */
{ X86_VENDOR_AMD, 0x100f62 }, /* DA-C2 */
{ X86_VENDOR_AMD, 0x100f63 }, /* DA-C3 */
{ X86_VENDOR_AMD, 0x100f80 }, /* HY-D0 */
{ X86_VENDOR_AMD, 0x100f81 }, /* HY-D1 */
{ X86_VENDOR_AMD, 0x100f91 }, /* HY-D1 */
{ X86_VENDOR_AMD, 0x100fa0 }, /* PH-E0 */
{ X86_VENDOR_AMD, 0x600f12 }, /* OR-B2 */
{ X86_VENDOR_AMD, 0x600f20 }, /* OR-C0 */
{ 0, 0 },
};
static const struct cpu_driver model_10xxx __cpu_driver = {
.ops = &cpu_dev_ops,
.id_table = cpu_table,
};

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src/cpu/amd/family_10h-family_15h/monotonic_timer.c
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/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
#include <timer.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <northbridge/amd/amdht/AsPsDefs.h>
static struct monotonic_counter {
int initialized;
uint32_t core_frequency;
struct mono_time time;
uint64_t last_value;
} mono_counter;
static inline uint64_t read_counter_msr(void)
{
msr_t counter_msr;
counter_msr = rdmsr(TSC_MSR);
return ((uint64_t)counter_msr.hi << 32) | (uint64_t)counter_msr.lo;
}
static void init_timer(void)
{
uint8_t model;
uint32_t cpuid_fms;
uint8_t cpufid;
uint8_t cpudid;
uint8_t boost_capable = 0;
/* Get CPU model */
cpuid_fms = cpuid_eax(0x80000001);
model = ((cpuid_fms & 0xf0000) >> 16) | ((cpuid_fms & 0xf0) >> 4);
/* Get boost capability */
if ((model == 0x8) || (model == 0x9)) { /* revision D */
boost_capable = (pci_read_config32(pcidev_on_root(0x18, 4),
0x15c) & 0x4) >> 2;
}
/* Set up TSC (BKDG v3.62 section 2.9.4)*/
msr_t msr = rdmsr(HWCR_MSR);
msr.lo |= 0x1000000;
wrmsr(HWCR_MSR, msr);
/* Get core Pstate 0 frequency in MHz */
msr = rdmsr(PSTATE_0_MSR + boost_capable);
cpufid = (msr.lo & 0x3f);
cpudid = (msr.lo & 0x1c0) >> 6;
mono_counter.core_frequency = (100 * (cpufid + 0x10)) / (0x01 << cpudid);
mono_counter.last_value = read_counter_msr();
mono_counter.initialized = 1;
}
void timer_monotonic_get(struct mono_time *mt)
{
uint64_t current_tick;
uint32_t usecs_elapsed = 0;
if (!mono_counter.initialized)
init_timer();
current_tick = read_counter_msr();
if (mono_counter.core_frequency != 0)
usecs_elapsed = (current_tick - mono_counter.last_value) / mono_counter.core_frequency;
/* Update current time and tick values only if a full tick occurred. */
if (usecs_elapsed) {
mono_time_add_usecs(&mono_counter.time, usecs_elapsed);
mono_counter.last_value = current_tick;
}
/* Save result. */
*mt = mono_counter.time;
}

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src/cpu/amd/family_10h-family_15h/powernow_acpi.c
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/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <option.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
#include <arch/acpigen.h>
#include <cpu/amd/powernow.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdfam10_sysconf.h>
#include <arch/cpu.h>
#include <northbridge/amd/amdht/AsPsDefs.h>
#include <northbridge/amd/amdmct/mct/mct.h>
#include <northbridge/amd/amdmct/amddefs.h>
#include <types.h>
static inline uint8_t is_fam15h(void)
{
uint8_t fam15h = 0;
uint32_t family;
family = cpuid_eax(0x80000001);
family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
if (family >= 0x6f)
/* Family 15h or later */
fam15h = 1;
return fam15h;
}
static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u32 *pstate_power,
u32 *pstate_latency, u32 *pstate_control,
u32 *pstate_status, int coreID,
uint8_t single_link)
{
int i;
struct cpuid_result cpuid1;
acpigen_write_empty_PCT();
acpigen_write_name("_PSS");
/* add later to total sum */
acpigen_write_package(pstate_num);
for (i = 0;i < pstate_num; i++)
acpigen_write_PSS_package(pstate_feq[i],
pstate_power[i],
pstate_latency[i],
pstate_latency[i],
pstate_control[i],
pstate_status[i]);
/* update the package size */
acpigen_pop_len();
/* Write PPC object */
acpigen_write_PPC(pstate_num);
/* Write PSD indicating coordination type */
if ((single_link) && (mctGetLogicalCPUID(0) & AMD_DR_GT_Bx)) {
/* Revision C or greater single-link processor */
cpuid1 = cpuid(0x80000008);
acpigen_write_PSD_package(0, (cpuid1.ecx & 0xff) + 1, SW_ALL);
} else {
/* Find the local APIC ID for the specified core ID */
struct device* cpu;
int cpu_index = 0;
for (cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC) ||
(cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER))
continue;
if (!cpu->enabled)
continue;
if (cpu_index == coreID)
break;
cpu_index++;
}
if (cpu)
acpigen_write_PSD_package(cpu->path.apic.apic_id, 1, SW_ANY);
}
}
static void write_cstates_for_core(int coreID)
{
/* Generate C state entries */
uint8_t cstate_count = 1;
acpi_cstate_t cstate;
if (is_fam15h()) {
cstate.ctype = 2;
cstate.latency = 100;
cstate.power = 0;
cstate.resource.space_id = ACPI_ADDRESS_SPACE_IO;
cstate.resource.bit_width = 8;
cstate.resource.bit_offset = 0;
cstate.resource.addrl = rdmsr(MSR_CSTATE_ADDRESS).lo + 1;
cstate.resource.addrh = 0;
cstate.resource.access_size = 1;
} else {
cstate.ctype = 2;
cstate.latency = 75;
cstate.power = 0;
cstate.resource.space_id = ACPI_ADDRESS_SPACE_IO;
cstate.resource.bit_width = 8;
cstate.resource.bit_offset = 0;
cstate.resource.addrl = rdmsr(MSR_CSTATE_ADDRESS).lo;
cstate.resource.addrh = 0;
cstate.resource.access_size = 1;
}
acpigen_write_CST_package(&cstate, cstate_count);
/* Find the local APIC ID for the specified core ID */
if (is_fam15h()) {
struct device* cpu;
int cpu_index = 0;
for (cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC) ||
(cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER))
continue;
if (!cpu->enabled)
continue;
if (cpu_index == coreID)
break;
cpu_index++;
}
if (cpu) {
/* TODO
* Detect dual core status and skip CSD generation if dual core is disabled
*/
/* Generate C state dependency entries */
acpigen_write_CSD_package((cpu->path.apic.apic_id >> 1) & 0x7f, 2, CSD_HW_ALL, 0);
}
}
}
/*
* For details of this algorithm, please refer to:
* Family 10h BDKG 3.62 page 69
* Family 15h BDKG 3.14 page 74
*
* WARNING: The core count algorithm below assumes that all processors
* are identical, with the same number of active cores. While the BKDG
* states the BIOS must enforce this coreboot does not currently do so.
* As a result it is possible that this code may break if an illegal
* processor combination is installed. If it does break please fix the
* code in the proper locations!
*/
void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
{
u8 processor_brand[49];
u32 *v;
struct cpuid_result cpuid1;
u16 Pstate_feq[10];
u32 Pstate_power[10];
u32 Pstate_latency[10];
u32 Pstate_control[10];
u32 Pstate_status[10];
u8 Pstate_num;
u8 cmp_cap;
u8 index;
msr_t msr;
uint8_t nvram;
uint8_t enable_c_states;
enable_c_states = 0;
#if CONFIG(HAVE_ACPI_TABLES)
if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS)
enable_c_states = !!nvram;
#endif
/* Get the Processor Brand String using cpuid(0x8000000x) command x=2,3,4 */
cpuid1 = cpuid(0x80000002);
v = (u32 *) processor_brand;
v[0] = cpuid1.eax;
v[1] = cpuid1.ebx;
v[2] = cpuid1.ecx;
v[3] = cpuid1.edx;
cpuid1 = cpuid(0x80000003);
v[4] = cpuid1.eax;
v[5] = cpuid1.ebx;
v[6] = cpuid1.ecx;
v[7] = cpuid1.edx;
cpuid1 = cpuid(0x80000004);
v[8] = cpuid1.eax;
v[9] = cpuid1.ebx;
v[10] = cpuid1.ecx;
v[11] = cpuid1.edx;
processor_brand[48] = 0;
printk(BIOS_INFO, "processor_brand=%s\n", processor_brand);
uint32_t dtemp;
uint8_t node_index;
uint8_t node_count;
uint8_t cores_per_node;
uint8_t total_core_count;
uint8_t fam15h;
uint8_t fam10h_rev_e = 0;
/* Detect Revision E processors via method used in fidvid.c */
if ((cpuid_edx(0x80000007) & CPB_MASK)
&& ((cpuid_ecx(0x80000008) & NC_MASK) == 5))
fam10h_rev_e = 1;
/*
* Based on the CPU socket type, cmp_cap and pwr_lmt, get the power limit.
* socket_type : 0x10 SocketF; 0x11 AM2/ASB1; 0x12 S1G1
* cmp_cap : 0x0 SingleCore; 0x1 DualCore; 0x2 TripleCore; 0x3 QuadCore; 0x4 QuintupleCore; 0x5 HexCore
*/
printk(BIOS_INFO, "Pstates algorithm ...\n");
fam15h = !!(mctGetLogicalCPUID(0) & AMD_FAM15_ALL);
/* Get number of cores */
if (fam15h) {
cmp_cap = pci_read_config32(pcidev_on_root(0x18, 5), 0x84) &
0xff;
} else {
dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xe8);
cmp_cap = (dtemp & 0x3000) >> 12;
if (mctGetLogicalCPUID(0) & (AMD_FAM10_REV_D | AMD_FAM15_ALL)) /* revision D or higher */
cmp_cap |= (dtemp & 0x8000) >> 13;
}
/* Get number of nodes */
dtemp = pci_read_config32(pcidev_on_root(0x18, 0), 0x60);
node_count = ((dtemp & 0x70) >> 4) + 1;
cores_per_node = cmp_cap + 1;
/* Compute total number of cores installed in system */
total_core_count = cores_per_node * node_count;
/* Get number of boost states */
uint8_t boost_count = 0;
dtemp = pci_read_config32(pcidev_on_root(0x18, 4), 0x15c);
if (fam10h_rev_e)
boost_count = (dtemp >> 2) & 0x1;
else if (mctGetLogicalCPUID(0) & AMD_FAM15_ALL)
boost_count = (dtemp >> 2) & 0x7;
/* See if the CPUID(0x80000007) returned EDX[7]==1b */
cpuid1 = cpuid(0x80000007);
if ((cpuid1.edx & 0x80) != 0x80) {
printk(BIOS_INFO, "No valid set of P-states\n");
return;
}
if (fam15h)
/* Set P_LVL2 P_BLK entry */
*(((uint8_t *)pcontrol_blk) + 0x04) =
(rdmsr(MSR_CSTATE_ADDRESS).lo + 1) & 0xff;
uint8_t pviModeFlag;
uint8_t Pstate_max;
uint8_t cpufid;
uint8_t cpudid;
uint8_t cpuvid;
uint8_t cpuidd;
uint8_t cpuidv;
uint8_t power_step_up;
uint8_t power_step_down;
uint8_t pll_lock_time;
uint32_t expanded_cpuidv;
uint32_t core_frequency;
uint32_t core_power;
uint32_t core_latency;
uint32_t core_voltage; /* multiplied by 10000 */
uint8_t single_link;
/* Determine if this is a PVI or SVI system */
dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xA0);
if (dtemp & PVI_MODE)
pviModeFlag = 1;
else
pviModeFlag = 0;
/* Get PSmax's index */
msr = rdmsr(PS_LIM_REG);
Pstate_max = (uint8_t) ((msr.lo >> PS_MAX_VAL_SHFT) & ((fam15h)?BIT_MASK_7:BIT_MASK_3));
/* Determine if all enabled Pstates have the same fidvid */
uint8_t i;
uint8_t cpufid_prev = (rdmsr(PSTATE_0_MSR).lo & 0x3f);
uint8_t all_enabled_cores_have_same_cpufid = 1;
for (i = 1; i < Pstate_max; i++) {
cpufid = rdmsr(PSTATE_0_MSR + i).lo & 0x3f;
if (cpufid != cpufid_prev) {
all_enabled_cores_have_same_cpufid = 0;
break;
}
}
/* Family 15h uses slightly different PSmax numbering */
if (fam15h)
Pstate_max++;
/* Populate tables with all Pstate information */
for (Pstate_num = 0; Pstate_num < Pstate_max; Pstate_num++) {
/* Get power state information */
msr = rdmsr(PSTATE_0_MSR + Pstate_num + boost_count);
cpufid = (msr.lo & 0x3f);
cpudid = (msr.lo & 0x1c0) >> 6;
cpuvid = (msr.lo & 0xfe00) >> 9;
cpuidd = (msr.hi & 0xff);
cpuidv = (msr.hi & 0x300) >> 8;
core_frequency = (100 * (cpufid + 0x10)) / (0x01 << cpudid);
if (pviModeFlag) {
if (cpuvid >= 0x20) {
core_voltage = 7625 - (((cpuvid - 0x20) * 10000) / 80);
} else {
core_voltage = 15500 - ((cpuvid * 10000) / 40);
}
} else {
cpuvid = cpuvid & 0x7f;
if (cpuvid >= 0x7c)
core_voltage = 0;
else
core_voltage = 15500 - ((cpuvid * 10000) / 80);
}
switch (cpuidv) {
case 0x0:
expanded_cpuidv = 1;
break;
case 0x1:
expanded_cpuidv = 10;
break;
case 0x2:
expanded_cpuidv = 100;
break;
case 0x3:
expanded_cpuidv = 1000;
break;
default:
printk(BIOS_ERR, "%s:%s:%d: Invalid cpuidv, "
"not generating pstate tables.\n",
__FILE__, __func__, __LINE__);
return;
}
core_power = (core_voltage * cpuidd) / (expanded_cpuidv * 10);
/* Calculate transition latency */
dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xD4);
power_step_up = (dtemp & 0xf000000) >> 24;
power_step_down = (dtemp & 0xf00000) >> 20;
dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xA0);
pll_lock_time = (dtemp & 0x3800) >> 11;
if (all_enabled_cores_have_same_cpufid)
core_latency = ((12 * power_step_down) + power_step_up) / 1000;
else
core_latency = (12 * (power_step_down + power_step_up) / 1000)
+ pll_lock_time;
Pstate_feq[Pstate_num] = core_frequency;
Pstate_power[Pstate_num] = core_power;
Pstate_latency[Pstate_num] = core_latency;
Pstate_control[Pstate_num] = Pstate_num;
Pstate_status[Pstate_num] = Pstate_num;
}
/* Print Pstate frequency, power, and latency */
for (index = 0; index < Pstate_num; index++) {
printk(BIOS_INFO, "Pstate_freq[%d] = %dMHz\t", index,
Pstate_feq[index]);
printk(BIOS_INFO, "Pstate_power[%d] = %dmw\n", index,
Pstate_power[index]);
printk(BIOS_INFO, "Pstate_latency[%d] = %dus\n", index,
Pstate_latency[index]);
}
/* Enter processor block scope */
char pscope[] = "\\_PR";
acpigen_write_scope(pscope);
for (index = 0; index < total_core_count; index++) {
/* Determine if this is a single-link processor */
node_index = 0x18 + (index / cores_per_node);
dtemp = pci_read_config32(pcidev_on_root(node_index, 0), 0x80);
single_link = !!(((dtemp & 0xff00) >> 8) == 0);
/* Enter processor core scope */
uint8_t plen_cur = plen;
uint32_t pcontrol_blk_cur = pcontrol_blk;
if ((onlyBSP) && (index != 0)) {
plen_cur = 0;
pcontrol_blk_cur = 0;
}
acpigen_write_processor(index, pcontrol_blk_cur, plen_cur);
/* Write P-state status and dependency objects */
write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_power,
Pstate_latency, Pstate_control, Pstate_status,
index, single_link);
/* Write C-state status and dependency objects */
if (fam15h && enable_c_states)
write_cstates_for_core(index);
/* Exit processor core scope */
acpigen_pop_len();
}
/* Exit processor block scope */
acpigen_pop_len();
}
void amd_powernow_update_fadt(acpi_fadt_t * fadt)
{
if (is_fam15h()) {
fadt->p_lvl2_lat = 101; /* NOTE: While the BKDG states this should
* be set to 100, there is no way to meet
* the other FADT requirements. I suspect
* there is an error in the BKDG for ACPI
* 1.x support; disable all FADT-based C
* states > 2... */
fadt->p_lvl3_lat = 1001;
fadt->flags |= 0x1 << 2; /* FLAGS.PROC_C1 = 1 */
fadt->flags |= 0x1 << 3; /* FLAGS.P_LVL2_UP = 1 */
} else {
fadt->cst_cnt = 0;
}
fadt->pstate_cnt = 0;
}

353
src/cpu/amd/family_10h-family_15h/processor_name.c
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@ -1,353 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* This code sets the Processor Name String for AMD64 CPUs.
*
* Revision Guide for AMD Family 10h Processors
* Publication # 41322 Revision: 3.17 Issue Date: February 2008
*/
#include <console/console.h>
#include <string.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pnp.h>
#include <device/pci_ops.h>
#include <stdlib.h>
#include <types.h>
/* The maximum length of CPU names is 48 bytes, including the final NULL byte.
* If you change these names your BIOS will _NOT_ pass the AMD validation and
* your mainboard will not be posted on the AMD Recommended Motherboard Website
*/
struct str_s {
u8 Pg;
u8 NC;
u8 String;
char const *value;
};
static const struct str_s String1_socket_F[] = {
{0x00, 0x01, 0x00, "Dual-Core AMD Opteron(tm) Processor 83"},
{0x00, 0x01, 0x01, "Dual-Core AMD Opteron(tm) Processor 23"},
{0x00, 0x03, 0x00, "Quad-Core AMD Opteron(tm) Processor 83"},
{0x00, 0x03, 0x01, "Quad-Core AMD Opteron(tm) Processor 23"},
{0x00, 0x05, 0x00, "Six-Core AMD Opteron(tm) Processor 84"},
{0x00, 0x05, 0x01, "Six-Core AMD Opteron(tm) Processor 24"},
{0x00, 0x03, 0x02, "Embedded AMD Opteron(tm) Processor 83"},
{0x00, 0x03, 0x03, "Embedded AMD Opteron(tm) Processor 23"},
{0x00, 0x03, 0x04, "Embedded AMD Opteron(tm) Processor 13"},
{0x00, 0x03, 0x05, "AMD Phenom(tm) FX-"},
{0x01, 0x01, 0x01, "Embedded AMD Opteron(tm) Processor"},
{0, 0, 0, NULL}
};
static const struct str_s String2_socket_F[] = {
{0x00, 0xFF, 0x02, " EE"},
{0x00, 0xFF, 0x0A, " SE"},
{0x00, 0xFF, 0x0B, " HE"},
{0x00, 0xFF, 0x0C, " EE"},
{0x00, 0xFF, 0x0D, " Quad-Core Processor"},
{0x00, 0xFF, 0x0F, ""},
{0x01, 0x01, 0x01, "GF HE"},
{0, 0, 0, NULL}
};
static const struct str_s String1_socket_AM2[] = {
{0x00, 0x00, 0x00, "AMD Athlon(tm) Processor LE-"},
{0x00, 0x00, 0x01, "AMD Sempron(tm) Processor LE-"},
{0x00, 0x00, 0x02, "AMD Sempron(tm) 1"},
{0x00, 0x00, 0x03, "AMD Athlon(tm) II 1"},
{0x00, 0x01, 0x00, "Dual-Core AMD Opteron(tm) Processor 13"},
{0x00, 0x01, 0x01, "AMD Athlon(tm)"},
{0x00, 0x01, 0x03, "AMD Athlon(tm) II X2 2"},
{0x00, 0x01, 0x04, "AMD Athlon(tm) II X2 B"},
{0x00, 0x01, 0x05, "AMD Athlon(tm) II X2"},
{0x00, 0x01, 0x07, "AMD Phenom(tm) II X2 5"},
{0x00, 0x01, 0x0A, "AMD Phenom(tm) II X2"},
{0x00, 0x01, 0x0B, "AMD Phenom(tm) II X2 B"},
{0x00, 0x02, 0x00, "AMD Phenom(tm)"},
{0x00, 0x02, 0x03, "AMD Phenom(tm) II X3 B"},
{0x00, 0x02, 0x04, "AMD Phenom(tm) II X3"},
{0x00, 0x02, 0x07, "AMD Athlon(tm) II X3 4"},
{0x00, 0x02, 0x08, "AMD Phenom(tm) II X3 7"},
{0x00, 0x02, 0x0A, "AMD Athlon(tm) II X3"},
{0x00, 0x03, 0x00, "Quad-Core AMD Opteron(tm) Processor 13"},
{0x00, 0x03, 0x01, "AMD Phenom(tm) FX-"},
{0x00, 0x03, 0x02, "AMD Phenom(tm)"},
{0x00, 0x03, 0x03, "AMD Phenom(tm) II X4 9"},
{0x00, 0x03, 0x04, "AMD Phenom(tm) II X4 8"},
{0x00, 0x03, 0x07, "AMD Phenom(tm) II X4 B"},
{0x00, 0x03, 0x08, "AMD Phenom(tm) II X4"},
{0x00, 0x03, 0x0A, "AMD Athlon(tm) II X4 6"},
{0x00, 0x03, 0x0F, "AMD Athlon(tm) II X4"},
{0, 0, 0, NULL}
};
static const struct str_s String2_socket_AM2[] = {
{0x00, 0x00, 0x00, "00"},
{0x00, 0x00, 0x01, "10"},
{0x00, 0x00, 0x02, "20"},
{0x00, 0x00, 0x03, "30"},
{0x00, 0x00, 0x04, "40"},
{0x00, 0x00, 0x05, "50"},
{0x00, 0x00, 0x06, "60"},
{0x00, 0x00, 0x07, "70"},
{0x00, 0x00, 0x08, "80"},
{0x00, 0x00, 0x09, "90"},
{0x00, 0x00, 0x09, " Processor"},
{0x00, 0x00, 0x09, "u Processor"},
{0x00, 0x01, 0x00, "00 Dual-Core Processor"},
{0x00, 0x01, 0x01, "00e Dual-Core Processor"},
{0x00, 0x01, 0x02, "00B Dual-Core Processor"},
{0x00, 0x01, 0x03, "50 Dual-Core Processor"},
{0x00, 0x01, 0x04, "50e Dual-Core Processor"},
{0x00, 0x01, 0x05, "50B Dual-Core Processor"},
{0x00, 0x01, 0x06, " Processor"},
{0x00, 0x01, 0x07, "e Processor"},
{0x00, 0x01, 0x09, "0 Processor"},
{0x00, 0x01, 0x0A, "0e Processor"},
{0x00, 0x01, 0x0B, "u Processor"},
{0x00, 0x02, 0x00, "00 Triple-Core Processor"},
{0x00, 0x02, 0x01, "00e Triple-Core Processor"},
{0x00, 0x02, 0x02, "00B Triple-Core Processor"},
{0x00, 0x02, 0x03, "50 Triple-Core Processor"},
{0x00, 0x02, 0x04, "50e Triple-Core Processor"},
{0x00, 0x02, 0x05, "50B Triple-Core Processor"},
{0x00, 0x02, 0x06, " Processor"},
{0x00, 0x02, 0x07, "e Processor"},
{0x00, 0x02, 0x09, "0e Processor"},
{0x00, 0x02, 0x0A, "0 Processor"},
{0x00, 0x03, 0x00, "00 Quad-Core Processor"},
{0x00, 0x03, 0x01, "00e Quad-Core Processor"},
{0x00, 0x03, 0x02, "00B Quad-Core Processor"},
{0x00, 0x03, 0x03, "50 Quad-Core Processor"},
{0x00, 0x03, 0x04, "50e Quad-Core Processor"},
{0x00, 0x03, 0x05, "50B Quad-Core Processor"},
{0x00, 0x03, 0x06, " Processor"},
{0x00, 0x03, 0x07, "e Processor"},
{0x00, 0x03, 0x09, "0e Processor"},
{0x00, 0x03, 0x0A, " SE"},
{0x00, 0x03, 0x0B, " HE"},
{0x00, 0x03, 0x0C, " EE"},
{0x00, 0x03, 0x0D, " Quad-Core Processor"},
{0x00, 0x03, 0x0E, "0 Processor"},
{0x00, 0xFF, 0x0F, ""},
{0, 0, 0, NULL}
};
static const struct str_s String1_socket_G34[] = {
{0x00, 0x07, 0x00, "AMD Opteron(tm) Processor 61"},
{0x00, 0x0B, 0x00, "AMD Opteron(tm) Processor 61"},
{0x01, 0x07, 0x01, "Embedded AMD Opteron(tm) Processor "},
{0, 0, 0, NULL}
};
static const struct str_s String2_socket_G34[] = {
{0x00, 0x07, 0x00, " HE"},
{0x00, 0x07, 0x01, " SE"},
{0x00, 0x0B, 0x00, " HE"},
{0x00, 0x0B, 0x01, " SE"},
{0x00, 0x0B, 0x0F, ""},
{0x01, 0x07, 0x01, " QS"},
{0x01, 0x07, 0x02, " KS"},
{0, 0, 0, NULL}
};
static const struct str_s String1_socket_C32[] = {
{0x00, 0x03, 0x00, "AMD Opteron(tm) Processor 41"},
{0x00, 0x05, 0x00, "AMD Opteron(tm) Processor 41"},
{0x01, 0x03, 0x01, "Embedded AMD Opteron(tm) Processor "},
{0x01, 0x05, 0x01, "Embedded AMD Opteron(tm) Processor "},
{0, 0, 0, NULL}
};
static const struct str_s String2_socket_C32[] = {
{0x00, 0x03, 0x00, " HE"},
{0x00, 0x03, 0x01, " EE"},
{0x00, 0x05, 0x00, " HE"},
{0x00, 0x05, 0x01, " EE"},
{0x01, 0x03, 0x01, "QS HE"},
{0x01, 0x03, 0x02, "LE HE"},
{0x01, 0x05, 0x01, "KX HE"},
{0x01, 0x05, 0x02, "GL EE"},
{0, 0, 0, NULL}
};
const char *unknown = "AMD Processor model unknown";
const char *unknown2 = " type unknown";
const char *sample = "AMD Engineering Sample";
const char *thermal = "AMD Thermal Test Kit";
static int strcpymax(char *dst, const char *src, int buflen)
{
int i;
for (i = 0; i < buflen && src[i]; i++)
dst[i] = src[i];
if (i >= buflen)
i--;
dst[i] = 0;
return i;
}
#define NAME_STRING_MAXLEN 48
int init_processor_name(void)
{
msr_t msr;
ssize_t i;
char program_string[NAME_STRING_MAXLEN];
u32 *p_program_string = (u32 *)program_string;
uint8_t fam15h = 0;
uint32_t family;
family = cpuid_eax(0x80000001);
family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
if (family >= 0x6f)
/* Family 15h or later */
fam15h = 1;
/* null the string */
memset(program_string, 0, sizeof(program_string));
if (fam15h) {
/* Family 15h or later */
uint32_t dword;
struct device *cpu_fn5_dev = pcidev_on_root(0x18, 5);
pci_write_config32(cpu_fn5_dev, 0x194, 0);
dword = pci_read_config32(cpu_fn5_dev, 0x198);
if (dword == 0) {
strcpymax(program_string, sample, sizeof(program_string));
} else {
/* Assemble the string from PCI configuration register contents */
for (i = 0; i < 12; i++) {
pci_write_config32(cpu_fn5_dev, 0x194, i);
p_program_string[i] = pci_read_config32(cpu_fn5_dev, 0x198);
}
/* Correctly place the null terminator */
for (i = (NAME_STRING_MAXLEN - 2); i > 0; i--) {
if (program_string[i] != 0x20)
break;
}
program_string[i + 1] = 0;
}
} else {
/* variable names taken from fam10 revision guide for clarity */
u32 BrandId; /* CPUID Fn8000_0001_EBX */
u8 String1; /* BrandID[14:11] */
u8 String2; /* BrandID[3:0] */
u8 Model; /* BrandID[10:4] */
u8 Pg; /* BrandID[15] */
u8 PkgTyp; /* BrandID[31:28] */
u8 NC; /* CPUID Fn8000_0008_ECX */
const char *processor_name_string = unknown;
int j = 0, str2_checkNC = 1;
const struct str_s *str, *str2;
/* Find out which CPU brand it is */
BrandId = cpuid_ebx(0x80000001);
String1 = (u8)((BrandId >> 11) & 0x0F);
String2 = (u8)((BrandId >> 0) & 0x0F);
Model = (u8)((BrandId >> 4) & 0x7F);
Pg = (u8)((BrandId >> 15) & 0x01);
PkgTyp = (u8)((BrandId >> 28) & 0x0F);
NC = (u8)(cpuid_ecx(0x80000008) & 0xFF);
if (!Model) {
processor_name_string = Pg ? thermal : sample;
goto done;
}
switch (PkgTyp) {
case 0: /* F1207 */
str = String1_socket_F;
str2 = String2_socket_F;
str2_checkNC = 0;
break;
case 1: /* AM2 */
str = String1_socket_AM2;
str2 = String2_socket_AM2;
break;
case 3: /* G34 */
str = String1_socket_G34;
str2 = String2_socket_G34;
str2_checkNC = 0;
break;
case 5: /* C32 */
str = String1_socket_C32;
str2 = String2_socket_C32;
break;
default:
goto done;
}
/* String1 */
for (i = 0; str[i].value; i++) {
if ((str[i].Pg == Pg) &&
(str[i].NC == NC) &&
(str[i].String == String1)) {
processor_name_string = str[i].value;
break;
}
}
if (!str[i].value)
goto done;
j = strcpymax(program_string, processor_name_string,
sizeof(program_string));
/* Translate Model from 01-99 to ASCII and put it on the end.
* Numbers less than 10 should include a leading zero, e.g., 09.*/
if (Model < 100 && j < sizeof(program_string) - 2) {
program_string[j++] = (Model / 10) + '0';
program_string[j++] = (Model % 10) + '0';
}
processor_name_string = unknown2;
/* String 2 */
for (i = 0; str2[i].value; i++) {
if ((str2[i].Pg == Pg) &&
((str2[i].NC == NC) || !str2_checkNC) &&
(str2[i].String == String2)) {
processor_name_string = str2[i].value;
break;
}
}
done:
strcpymax(&program_string[j], processor_name_string,
sizeof(program_string) - j);
}
printk(BIOS_DEBUG, "CPU model: %s\n", program_string);
for (i = 0; i < 6; i++) {
msr.lo = p_program_string[(2 * i) + 0];
msr.hi = p_program_string[(2 * i) + 1];
wrmsr_amd(0xC0010030 + i, msr);
}
return 0;
}

94
src/cpu/amd/family_10h-family_15h/ram_calc.c
View File

@ -1,94 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <cbmem.h>
#include "ram_calc.h"
static inline uint8_t is_fam15h(void)
{
uint8_t fam15h = 0;
uint32_t family;
family = cpuid_eax(0x80000001);
family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
if (family >= 0x6f)
/* Family 15h or later */
fam15h = 1;
return fam15h;
}
uint64_t get_uma_memory_size(uint64_t topmem)
{
uint64_t uma_size = 0;
if (CONFIG(GFXUMA)) {
/* refer to UMA Size Consideration in 780 BDG. */
if (topmem >= 0x40000000) /* 1GB and above system memory */
uma_size = 0x10000000; /* 256M recommended UMA */
else if (topmem >= 0x20000000) /* 512M - 1023M system memory */
uma_size = 0x8000000; /* 128M recommended UMA */
else if (topmem >= 0x10000000) /* 256M - 511M system memory */
uma_size = 0x4000000; /* 64M recommended UMA */
}
return uma_size;
}
uint64_t get_cc6_memory_size()
{
uint8_t enable_cc6;
uint64_t cc6_size = 0;
if (is_fam15h()) {
enable_cc6 = 0;
#if ENV_PCI_SIMPLE_DEVICE
if (pci_read_config32(PCI_DEV(0, 0x18, 2), 0x118) & (0x1 << 18))
enable_cc6 = 1;
#else
struct device *dct_dev = pcidev_on_root(0x18, 2);
if (pci_read_config32(dct_dev, 0x118) & (0x1 << 18))
enable_cc6 = 1;
#endif
if (enable_cc6) {
/* Preserve the maximum possible CC6 save region
* This needs to be kept in sync with
* amdfam10_domain_read_resources() in northbridge.c
*/
cc6_size = 0x8000000;
}
}
return cc6_size;
}
void *cbmem_top_chipset(void)
{
uint32_t topmem = rdmsr(TOP_MEM).lo;
return (void *) topmem - get_uma_memory_size(topmem) - get_cc6_memory_size();
}

20
src/cpu/amd/family_10h-family_15h/ram_calc.h
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@ -1,20 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _AMD_MODEL_10XXX_RAM_CALC_H_
#define _AMD_MODEL_10XXX_RAM_CALC_H_
uint64_t get_uma_memory_size(uint64_t topmem);
uint64_t get_cc6_memory_size(void);
#endif

36
src/cpu/amd/family_10h-family_15h/tsc_freq.c
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@ -1,36 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/tsc.h>
unsigned long tsc_freq_mhz(void)
{
msr_t msr;
uint8_t cpufid;
uint8_t cpudid;
/* On Family 10h/15h CPUs the TSC increments
* at the P0 clock rate. Read the P0 clock
* frequency from the P0 MSR and convert
* to MHz. See also the Family 15h BKDG
* Rev. 3.14 page 569.
*/
msr = rdmsr(PSTATE_0_MSR);
cpufid = (msr.lo & 0x3f);
cpudid = (msr.lo & 0x1c0) >> 6;
return (100 * (cpufid + 0x10)) / (0x01 << cpudid);
}

70
src/cpu/amd/family_10h-family_15h/update_microcode.c
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@ -1,70 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <cpu/amd/microcode.h>
struct id_mapping {
uint32_t orig_id;
uint16_t new_id;
};
static u16 get_equivalent_processor_rev_id(u32 orig_id) {
static const struct id_mapping id_mapping_table[] = {
/* Family 10h */
{ 0x100f00, 0x1000 },
{ 0x100f01, 0x1000 },
{ 0x100f02, 0x1000 },
{ 0x100f20, 0x1020 },
{ 0x100f21, 0x1020 }, /* DR-B1 */
{ 0x100f2A, 0x1020 }, /* DR-BA */
{ 0x100f22, 0x1022 }, /* DR-B2 */
{ 0x100f23, 0x1022 }, /* DR-B3 */
{ 0x100f42, 0x1041 }, /* RB-C2 */
{ 0x100f43, 0x1043 }, /* RB-C3 */
{ 0x100f52, 0x1041 }, /* BL-C2 */
{ 0x100f62, 0x1062 }, /* DA-C2 */
{ 0x100f63, 0x1043 }, /* DA-C3 */
{ 0x100f81, 0x1081 }, /* HY-D1 */
{ 0x100f91, 0x1081 }, /* HY-D1 */
{ 0x100fa0, 0x10A0 }, /* PH-E0 */
/* Family 15h */
{ 0x600f12, 0x6012 }, /* OR-B2 */
{ 0x600f20, 0x6020 }, /* OR-C0 */
/* Array terminator */
{ 0xffffff, 0x0000 },
};
u32 new_id;
int i;
new_id = 0;
for (i = 0; id_mapping_table[i].orig_id != 0xffffff; i++) {
if (id_mapping_table[i].orig_id == orig_id) {
new_id = id_mapping_table[i].new_id;
break;
}
}
return new_id;
}
void update_microcode(u32 cpu_deviceid)
{
u32 equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid);
amd_update_microcode_from_cbfs(equivalent_processor_rev_id);
}

1
src/cpu/amd/quadcore/Makefile.inc
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@ -1 +0,0 @@
ramstage-y += amd_sibling.c

118
src/cpu/amd/quadcore/amd_sibling.c
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@ -1,118 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <cpu/x86/lapic.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
#include <smp/spinlock.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <cpu/amd/amdfam10_sysconf.h>
extern struct device *get_node_pci(u32 nodeid, u32 fn);
#if 0
static int first_time = 1;
#endif
#include "quadcore_id.c"
static u32 get_max_siblings(u32 nodes)
{
struct device *dev;
u32 nodeid;
u32 siblings = 0;
//get max siblings from all the nodes
for (nodeid = 0; nodeid < nodes; nodeid++) {
int j;
dev = get_node_pci(nodeid, 3);
j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
if (siblings < j)
siblings = j;
}
return siblings;
}
static void enable_apic_ext_id(u32 nodes)
{
struct device *dev;
u32 nodeid;
//enable APIC_EXIT_ID all the nodes
for (nodeid = 0; nodeid < nodes; nodeid++) {
u32 val;
dev = get_node_pci(nodeid, 0);
val = pci_read_config32(dev, 0x68);
val |= (1 << 17)|(1 << 18);
pci_write_config32(dev, 0x68, val);
}
}
u32 get_apicid_base(u32 ioapic_num)
{
u32 apicid_base;
u32 siblings;
u32 nb_cfg_54;
u32 disable_siblings = !CONFIG(LOGICAL_CPUS);
get_option(&disable_siblings, "multi_core");
siblings = get_max_siblings(sysconf.nodes);
if (sysconf.bsp_apicid > 0) {
// IOAPIC could start from 0
return 0;
} else if (sysconf.enabled_apic_ext_id) {
// enabled ext id but bsp = 0
return 1;
}
nb_cfg_54 = read_nb_cfg_54();
//Construct apicid_base
if ((!disable_siblings) && (siblings > 0)) {
/* for 8 way dual core, we will used up apicid 16:16, actually
16 is not allowed by current kernel and the kernel will try
to get one that is small than 16 to make IOAPIC work. I don't
know when the kernel can support 256 APIC id.
(APIC_EXT_ID is enabled) */
//4:10 for two way 8:12 for four way 16:16 for eight way
//Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes
//for better consistency?
apicid_base = nb_cfg_54 ? (siblings+1) * sysconf.nodes :
8 * siblings + sysconf.nodes;
} else {
apicid_base = sysconf.nodes;
}
if ((apicid_base+ioapic_num-1) > 0xf) {
// We need to enable APIC EXT ID
printk(BIOS_SPEW, "if the IOAPIC device doesn't support 256 APIC id,\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for IOAPIC\n");
enable_apic_ext_id(sysconf.nodes);
}
return apicid_base;
}

146
src/cpu/amd/quadcore/quadcore.c
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@ -1,146 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/cpu.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
#if CONFIG(HAVE_OPTION_TABLE)
#include "option_table.h"
#endif
#include "cpu/amd/quadcore/quadcore_id.c"
u32 get_core_num_in_bsp(u32 nodeid)
{
u32 dword;
if (is_fam15h()) {
/* Family 15h moved CmpCap to F5x84 [7:0] */
dword = pci_read_config32(NODE_PCI(nodeid, 5), 0x84);
dword &= 0xff;
} else {
dword = pci_read_config32(NODE_PCI(nodeid, 3), 0xe8);
dword >>= 12;
/* Bit 15 is CmpCap[2] since Revision D. */
if ((cpuid_ecx(0x80000008) & 0xff) > 3)
dword = ((dword & 8) >> 1) | (dword & 3);
else
dword &= 3;
}
return dword;
}
u8 set_apicid_cpuid_lo(void)
{
// set the NB_CFG[54]=1; why the OS will be happy with that ???
msr_t msr;
msr = rdmsr(NB_CFG_MSR);
msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo
wrmsr(NB_CFG_MSR, msr);
return 1;
}
void real_start_other_core(uint32_t nodeid, uint32_t cores)
{
ssize_t i;
uint32_t dword;
printk(BIOS_DEBUG,
"Start other core - nodeid: %02x cores: %02x\n", nodeid, cores);
/* set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4
accesses and error logging to core0 */
dword = pci_read_config32(NODE_PCI(nodeid, 3), 0x44);
dword |= 1 << 30; /* SyncFloodOnDramAdrParErr=1 */
dword |= 1 << 27; /* NbMcaToMstCpuEn=1 */
dword |= 1 << 21; /* SyncFloodOnAnyUcErr=1 */
dword |= 1 << 20; /* SyncFloodOnWDT=1 */
dword |= 1 << 2; /* SyncFloodOnDramUcEcc=1 */
pci_write_config32(NODE_PCI(nodeid, 3), 0x44, dword);
if (is_fam15h()) {
uint32_t core_activation_flags = 0;
uint32_t active_cores = 0;
/* Set PCI_DEV(0, 0x18+nodeid, 0),
* 0x1dc bits 7:1 to start cores
*/
dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x1dc);
for (i = 1; i < cores + 1; i++)
core_activation_flags |= 1 << i;
/* Start the first core of each compute unit */
active_cores |= core_activation_flags & 0x55;
pci_write_config32(NODE_PCI(nodeid, 0), 0x1dc, dword
| active_cores);
/* Each core shares a single set of MTRR registers with
* another core in the same compute unit, therefore, it
* is important that one core in each CU starts in advance
* of the other in order to avoid one core stomping all over
* the other core's settings.
*/
/* Wait for the first core of each compute unit to start... */
for (i = 1; i < cores + 1; i++) {
if (!(i & 0x1)) {
uint32_t ap_apicid =
get_boot_apic_id(nodeid, i);
/* Timeout */
wait_cpu_state(ap_apicid, F10_APSTATE_ASLEEP,
F10_APSTATE_ASLEEP);
}
}
/* Start the second core of each compute unit */
active_cores |= core_activation_flags & 0xaa;
pci_write_config32(NODE_PCI(nodeid, 0), 0x1dc, dword |
active_cores);
} else {
// set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1
dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x68);
dword |= 1 << 5;
pci_write_config32(NODE_PCI(nodeid, 0), 0x68, dword);
if (cores > 1) {
dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x168);
for (i = 0; i < cores - 1; i++)
dword |= 1 << i;
pci_write_config32(NODE_PCI(nodeid, 0), 0x168, dword);
}
}
}
#if (!CONFIG(CPU_AMD_MODEL_10XXX))
//it is running on core0 of node0
static void start_other_cores(void)
{
u32 nodes;
u32 nodeid;
// disable multi_core
if (read_option(multi_core, 0) != 0) {
printk(BIOS_DEBUG, "Skip additional core init\n");
return;
}
nodes = get_nodes();
for (nodeid = 0; nodeid < nodes; nodeid++) {
u32 cores = get_core_num_in_bsp(nodeid);
printk(BIOS_DEBUG, "init node: %02x cores: %02x pass 1\n",
nodeid, cores);
if (cores > 0)
real_start_other_core(nodeid, cores);
}
}
#endif

152
src/cpu/amd/quadcore/quadcore_id.c
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@ -1,152 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/cpu.h>
#include <cpu/amd/msr.h>
#include <cpu/amd/multicore.h>
#include <device/pci_ops.h>
//called by bus_cpu_scan too
u32 read_nb_cfg_54(void)
{
msr_t msr;
msr = rdmsr(NB_CFG_MSR);
return (msr.hi >> (54-32)) & 1;
}
u32 get_initial_apicid(void)
{
return (cpuid_ebx(1) >> 24) & 0xff;
}
/* Called by amd_siblings (ramstage) as well */
struct node_core_id get_node_core_id(u32 nb_cfg_54)
{
struct node_core_id id;
uint8_t apicid;
uint8_t fam15h = 0;
uint8_t rev_gte_d = 0;
uint8_t dual_node = 0;
uint32_t f3xe8;
uint32_t family;
uint32_t model;
#if ENV_PCI_SIMPLE_DEVICE
f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8);
#else
f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8);
#endif
family = model = cpuid_eax(0x80000001);
model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4);
family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
if (family >= 0x6f) {
/* Family 15h or later */
fam15h = 1;
nb_cfg_54 = 1;
}
if ((model >= 0x8) || fam15h)
/* Revision D or later */
rev_gte_d = 1;
if (rev_gte_d)
/* Check for dual node capability */
if (f3xe8 & 0x20000000)
dual_node = 1;
/* Get the apicid via cpuid(1) ebx[31:24]
* The apicid format varies based on processor revision
*/
apicid = (cpuid_ebx(1) >> 24) & 0xff;
if (nb_cfg_54) {
if (fam15h && dual_node) {
id.coreid = apicid & 0x1f;
id.nodeid = (apicid & 0x60) >> 5;
} else if (fam15h && !dual_node) {
id.coreid = apicid & 0xf;
id.nodeid = (apicid & 0x70) >> 4;
} else if (rev_gte_d && dual_node) {
id.coreid = apicid & 0xf;
id.nodeid = (apicid & 0x30) >> 4;
} else if (rev_gte_d && !dual_node) {
id.coreid = apicid & 0x7;
id.nodeid = (apicid & 0x38) >> 3;
} else {
id.coreid = apicid & 0x3;
id.nodeid = (apicid & 0x1c) >> 2;
}
} else {
if (rev_gte_d && dual_node) {
id.coreid = (apicid & 0xf0) >> 4;
id.nodeid = apicid & 0x3;
} else if (rev_gte_d && !dual_node) {
id.coreid = (apicid & 0xe0) >> 5;
id.nodeid = apicid & 0x7;
} else {
id.coreid = (apicid & 0x60) >> 5;
id.nodeid = apicid & 0x7;
}
}
if (fam15h && dual_node) {
/* coreboot expects each separate processor die to be on a
* different nodeid.
* Since the code above returns nodeid 0 even on
* internal node 1 some fixup is needed...
*/
uint32_t f5x84;
uint8_t core_count;
#if ENV_PCI_SIMPLE_DEVICE
f5x84 = pci_read_config32(NODE_PCI(0, 5), 0x84);
#else
f5x84 = pci_read_config32(get_node_pci(0, 5), 0x84);
#endif
core_count = (f5x84 & 0xff) + 1;
id.nodeid = id.nodeid * 2;
if (id.coreid >= core_count) {
id.nodeid += 1;
id.coreid = id.coreid - core_count;
}
} else if (rev_gte_d && dual_node) {
/* coreboot expects each separate processor die to be on a
* different nodeid.
* Since the code above returns nodeid 0 even on
* internal node 1 some fixup is needed...
*/
uint8_t core_count = (((f3xe8 & 0x00008000) >> 13) |
((f3xe8 & 0x00003000) >> 12)) + 1;
id.nodeid = id.nodeid * 2;
if (id.coreid >= core_count) {
id.nodeid += 1;
id.coreid = id.coreid - core_count;
}
}
return id;
}
#ifdef UNUSED_CODE
static u32 get_core_num(void)
{
return (cpuid_ecx(0x80000008) & 0xff);
}
#endif
struct node_core_id get_node_core_id_x(void)
{
return get_node_core_id(read_nb_cfg_54());
}

29
src/cpu/amd/socket_AM2r2/Kconfig
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@ -1,29 +0,0 @@
config CPU_AMD_SOCKET_AM2R2
bool
select CPU_AMD_MODEL_10XXX
select PCI_IO_CFG_EXT
select X86_AMD_FIXED_MTRRS
if CPU_AMD_SOCKET_AM2R2
config CPU_SOCKET_TYPE
hex
default 0x11
config EXT_RT_TBL_SUPPORT
bool
default n
config CBB
hex
default 0x0
config CDB
hex
default 0x18
config XIP_ROM_SIZE
hex
default 0x80000
endif

13
src/cpu/amd/socket_AM2r2/Makefile.inc
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@ -1,13 +0,0 @@
subdirs-y += ../family_10h-family_15h
subdirs-y += ../quadcore
subdirs-y += ../mtrr
subdirs-y += ../microcode
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/pae
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/smm
subdirs-y += ../smm
cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc

29
src/cpu/amd/socket_AM3/Kconfig
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@ -1,29 +0,0 @@
config CPU_AMD_SOCKET_AM3
bool
select CPU_AMD_MODEL_10XXX
select PCI_IO_CFG_EXT
select X86_AMD_FIXED_MTRRS
if CPU_AMD_SOCKET_AM3
config CPU_SOCKET_TYPE
hex
default 0x11
config EXT_RT_TBL_SUPPORT
bool
default n
config CBB
hex
default 0x0
config CDB
hex
default 0x18
config XIP_ROM_SIZE
hex
default 0x80000
endif

13
src/cpu/amd/socket_AM3/Makefile.inc
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@ -1,13 +0,0 @@
subdirs-y += ../family_10h-family_15h
subdirs-y += ../quadcore
subdirs-y += ../mtrr
subdirs-y += ../microcode
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/pae
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/smm
subdirs-y += ../smm
cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc

29
src/cpu/amd/socket_ASB2/Kconfig
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@ -1,29 +0,0 @@
config CPU_AMD_SOCKET_ASB2
bool
select CPU_AMD_MODEL_10XXX
select PCI_IO_CFG_EXT
select X86_AMD_FIXED_MTRRS
if CPU_AMD_SOCKET_ASB2
config CPU_SOCKET_TYPE
hex
default 0x13
config EXT_RT_TBL_SUPPORT
bool
default n
config CBB
hex
default 0x0
config CDB
hex
default 0x18
config XIP_ROM_SIZE
hex
default 0x80000
endif

13
src/cpu/amd/socket_ASB2/Makefile.inc
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@ -1,13 +0,0 @@
subdirs-y += ../family_10h-family_15h
subdirs-y += ../quadcore
subdirs-y += ../mtrr
subdirs-y += ../microcode
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/pae
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/smm
subdirs-y += ../smm
cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc

29
src/cpu/amd/socket_C32/Kconfig
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@ -1,29 +0,0 @@
config CPU_AMD_SOCKET_C32_NON_AGESA
bool
select CPU_AMD_MODEL_10XXX
select PCI_IO_CFG_EXT
select X86_AMD_FIXED_MTRRS
if CPU_AMD_SOCKET_C32_NON_AGESA
config CPU_SOCKET_TYPE
hex
default 0x14
config EXT_RT_TBL_SUPPORT
bool
default n
config CBB
hex
default 0x0
config CDB
hex
default 0x18
config XIP_ROM_SIZE
hex
default 0x80000
endif

13
src/cpu/amd/socket_C32/Makefile.inc
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@ -1,13 +0,0 @@
subdirs-y += ../family_10h-family_15h
subdirs-y += ../quadcore
subdirs-y += ../mtrr
subdirs-y += ../microcode
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/pae
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/smm
subdirs-y += ../smm
cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc

29
src/cpu/amd/socket_FM2/Kconfig
View File

@ -1,29 +0,0 @@
config CPU_AMD_SOCKET_FM2_NON_AGESA
bool
select CPU_AMD_MODEL_10XXX
select PCI_IO_CFG_EXT
select X86_AMD_FIXED_MTRRS
if CPU_AMD_SOCKET_FM2_NON_AGESA
config CPU_SOCKET_TYPE
hex
default 0x16
config EXT_RT_TBL_SUPPORT
bool
default n
config CBB
hex
default 0x0
config CDB
hex
default 0x18
config XIP_ROM_SIZE
hex
default 0x80000
endif

13
src/cpu/amd/socket_FM2/Makefile.inc
View File

@ -1,13 +0,0 @@
subdirs-y += ../family_10h-family_15h
subdirs-y += ../quadcore
subdirs-y += ../mtrr
subdirs-y += ../microcode
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/pae
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/smm
subdirs-y += ../smm
cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc

29
src/cpu/amd/socket_F_1207/Kconfig
View File

@ -1,29 +0,0 @@
config CPU_AMD_SOCKET_F_1207
bool
select CPU_AMD_MODEL_10XXX
select PCI_IO_CFG_EXT
select X86_AMD_FIXED_MTRRS
if CPU_AMD_SOCKET_F_1207
config CPU_SOCKET_TYPE
hex
default 0x10
config EXT_RT_TBL_SUPPORT
bool
default n
config CBB
hex
default 0x0
config CDB
hex
default 0x18
config XIP_ROM_SIZE
hex
default 0x80000
endif

13
src/cpu/amd/socket_F_1207/Makefile.inc
View File

@ -1,13 +0,0 @@
subdirs-y += ../family_10h-family_15h
subdirs-y += ../quadcore
subdirs-y += ../mtrr
subdirs-y += ../microcode
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/pae
subdirs-y += ../../x86/smm
subdirs-y += ../smm
cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc

29
src/cpu/amd/socket_G34/Kconfig
View File

@ -1,29 +0,0 @@
config CPU_AMD_SOCKET_G34_NON_AGESA
bool
select CPU_AMD_MODEL_10XXX
select PCI_IO_CFG_EXT
select X86_AMD_FIXED_MTRRS
if CPU_AMD_SOCKET_G34_NON_AGESA
config CPU_SOCKET_TYPE
hex
default 0x15
config EXT_RT_TBL_SUPPORT
bool
default n
config CBB
hex
default 0x0
config CDB
hex
default 0x18
config XIP_ROM_SIZE
hex
default 0x80000
endif

14
src/cpu/amd/socket_G34/Makefile.inc
View File

@ -1,14 +0,0 @@
ramstage-y += socket_G34.c
subdirs-y += ../family_10h-family_15h
subdirs-y += ../quadcore
subdirs-y += ../mtrr
subdirs-y += ../microcode
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/pae
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/smm
subdirs-y += ../smm
cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc

18
src/cpu/amd/socket_G34/socket_G34.c
View File

@ -1,18 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
struct chip_operations cpu_amd_socket_G34_ops = {
CHIP_NAME("socket G34")
};

2
src/cpu/x86/lapic/lapic_cpu_init.c
View File

@ -142,9 +142,7 @@ static int lapic_start_cpu(unsigned long apicid)
}
return 0;
}
#if !CONFIG(CPU_AMD_MODEL_10XXX)
mdelay(10);
#endif
printk(BIOS_SPEW, "Deasserting INIT.\n");