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mb/google/sarien: Disable unused GPIOs 

These 4 GPIOs are being disconnected in the next board so use the
board ID to configure these pins as not connected to ensure
they do not cause leakage.

Also remove the ACPI _PTS S5 code that was configuring the GPIOs.
This does mean they will cause small leakage in S5 on existing boards,
but it will not affect the new boards.

BUG=b:132393441
TEST=boot on sarien with fake board ID and ensure that coreboot
configures these pads as expected.

Change-Id: I6ac04b9a635829811a09aeab7cba3bb58cfcff47
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
This commit is contained in:
Duncan Laurie 2019-06-13 10:46:54 -07:00 committed by Duncan Laurie
parent 7945f75417
commit de666dc9b8
3 changed files with 12 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/mainboard/google/sarien/ramstage.c
View File

@ -14,6 +14,7 @@
*/
#include <arch/acpi.h>
#include <boardid.h>
#include <drivers/vpd/vpd.h>
#include <smbios.h>
#include <soc/gpio.h>
@ -60,6 +61,13 @@ void smbios_fill_dimm_locator(const struct dimm_info *dimm,
}
#endif
static const struct pad_config gpio_unused[] = {
/* SUSWARN# */ PAD_NC(GPP_A13, NONE),
/* SUSACK# */ PAD_NC(GPP_A15, NONE),
/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE),
/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE),
};
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
const struct pad_config *gpio_table;
@ -67,6 +75,10 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
gpio_table = variant_gpio_table(&num_gpios);
cnl_configure_pads(gpio_table, num_gpios);
/* Disable unused pads for devices with board ID > 2 */
if (board_id() > 2)
gpio_configure_pads(gpio_unused, ARRAY_SIZE(gpio_unused));
}
static void mainboard_enable(struct device *dev)

9
src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl
View File

@ -15,8 +15,6 @@
#define CAM_EN GPP_B11 /* Active low */
#define TS_PD GPP_E7
#define SSD_EN GPP_H13
#define SSD_RST GPP_H12
/* Method called from LPIT prior to enter s0ix state */
Method (MS0X, 1)
@ -37,13 +35,6 @@ Method (MPTS, 1)
/* Clear touch screen pd pin to avoid leakage */
\_SB.PCI0.CTXS (TS_PD)
/* Clear SSD EN adn RST pin to avoid leakage */
If (Arg0 == 5) {
\_SB.PCI0.CTXS (SSD_RST)
Sleep(1)
\_SB.PCI0.CTXS (SSD_EN)
}
}
/* Method called from _WAK prior to wakeup */

9
src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl
View File

@ -15,8 +15,6 @@
#define CAM_EN GPP_B11 /* Active low */
#define TS_PD GPP_E7
#define SSD_EN GPP_H13
#define SSD_RST GPP_H12
/* Method called from LPIT prior to enter s0ix state */
Method (MS0X, 1)
@ -37,13 +35,6 @@ Method (MPTS, 1)
/* Clear touch screen pd pin to avoid leakage */
\_SB.PCI0.CTXS (TS_PD)
/* Clear SSD EN adn RST pin to avoid leakage */
If (Arg0 == 5) {
\_SB.PCI0.CTXS (SSD_RST)
Sleep(1)
\_SB.PCI0.CTXS (SSD_EN)
}
}
/* Method called from _WAK prior to wakeup */